Netlist::Port(3)

okay so bestie 💖 welcome to Netlist::Port(3) from the User Contributed Perl Documentation — she's a Perl manual page, she's highkey iconic, and she's here to explain the port object for a Verilog module. grab a strawberry 🍓 and let's get into it.

🌸 NAME 🌸

Verilog::Netlist::Port - Port for a Verilog Module. it's giving port object realness, periodt. 👑

✨ SYNOPSIS ✨

the vibe is literally:

use Verilog::Netlist;

...
my $port = $module->find_port('pinname');
print $port->name;

💅 DESCRIPTION 💅

a Verilog::Netlist::Port object is created by Verilog::Netlist::Module for every port connection in the module. that's lowkey the origin story, no cap. 🦋

🫶 ACCESSORS 🫶

see also Verilog::Netlist::Subclass for additional accessors and methods. iykyk. ✨

• $self->array — any array declaration for the port. important caveat: this only applies to Verilog 1995 style ports, which can declare port bits independently from the signal declarations. when you're using Verilog 2001 style ports, see the matching net declaration's data_type, msb and lsb methods instead, for example "$module-"find_net($port->name)->data_type>. slay, but read the caveat. 💅
• $self->comment — returns any comments following the definition. for those comments to be retained, keep_comments=>1 must be passed to Verilog::Netlist::new. that flag is the whole vibe check. 🎀
• $self->data_type — the SystemVerilog data type of the port. she's giving type info. 🦋
• $self->direction — the direction of the port: "in", "out", or "inout". the way that she just tells you which way the signal is going? obsessed. 🌈
• $self->module — reference to the Verilog::Netlist::Module the port is in. main character container energy. 👑
• $self->name — the name of the port. literally just her name. 💖
• $self->net — reference to the Verilog::Netlist::Net the port connects to. only valid after the netlist is linked, so don't jump the gun bestie. ⭐
• $self->type — approximately an alias of data_type for backward compatibility. do not use for new applications. that's a warning, fr fr. 💀

🔥 MEMBER FUNCTIONS 🔥

again, see also Verilog::Netlist::Subclass for additional accessors and methods. 🫶

• $self->dump — prints debugging information for this port. debugging slay, no notes 😭. 🐛✨

🧚 DISTRIBUTION 🧚

Verilog-Perl is part of the <https://www.veripool.org/> free Verilog EDA software tool suite. the latest version is available from CPAN and from <https://www.veripool.org/verilog-perl>. ngl, that's the moment. 🔥

Copyright 2000-2024 by Wilson Snyder. this package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. free software license moment 🌈

👑 AUTHORS 👑

Wilson Snyder <wsnyder@wsnyder.org> — the author, the icon, the main character. 💌

🌟 SEE ALSO 🌟

Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist — go read these next, bestie. iykyk. 🦋

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mwah 💋 this page came from perl v5.42.0, dated 2025-07-25, and its footer is still serving Netlist::Port(3). bye bestie, go slay your netlist. 🫶💖