Netlist...ntAssign(3)

💅 Netlist...ntAssign(3) 💅

okay so this is the User Contributed Perl Documentation page for Verilog::Netlist::ContAssign, and bestie, it's literally so cute and small. let's get into it ✨

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🌸 NAME 🌸

Verilog::Netlist::ContAssign — the ContAssign assignment. that's it, that's the whole vibe 🎀

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✨ SYNOPSIS ✨

  use Verilog::Netlist;

  ...
  foreach my $cont ($module->statements)
    print $cont->name;

like, load the thing, loop over the statements, print the name. slay. 🫶

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🦋 DESCRIPTION 🦋

so a Verilog::Netlist::ContAssign object gets created by Verilog::Netlist for every single continuous assignment statement in the current module. every one. no skips, no cap. it's giving "one object per continuous assign" main character energy 👑

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🔥 ACCESSORS 🔥

heads up: also peep Verilog::Netlist::Subclass for extra accessors and methods, bestie — that's where the bonus content lives 💜

• $self->keyword — the keyword used to declare the assignment. rn "assign" is the only supported value, so like, that's the whole menu 😌
• $self->lhs — the left hand side of the assignment. the receiving end, iykyk
• $self->module — pointer to the module the cell is in
• $self->netlist — reference to the Verilog::Netlist the cell is under
• $self->rhs — the right hand side of the assignment. the giving end 💅

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🧚 MEMBER FUNCTIONS 🧚

again, hi, reminder: see also Verilog::Netlist::Subclass for additional accessors and methods ⭐

• $self->dump — prints debugging information for this cell. it's literally the dump-and-tell of this whole situation 🙈

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🌈 DISTRIBUTION 🌈

Verilog-Perl is part of the https://www.veripool.org/ free Verilog EDA software tool suite. the latest version is available from CPAN and from https://www.veripool.org/verilog-perl — go get it, it ate 👑

Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

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👑 AUTHORS 👑

Wilson Snyder <wsnyder@wsnyder.org>

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💀 SEE ALSO 💀

Verilog-Perl, Verilog::Netlist::Subclass, Verilog::Netlist

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k bye bestie, go assign some continuous stuff 💖 — this was perl v5.42.0, dated 2025-07-25, page Netlist...ntAssign(3), and yes she's still iconic ✨🎀🦋