Netlist::Module(3)

🌸 NAME 🌸

okay so this is Netlist::Module(3), a page from the User Contributed Perl Documentation crew, and it's literally about Verilog::Netlist::Module — Module within a Verilog Netlist. periodt 💅

🦋 SYNOPSIS 🦋

the synopsis vibe is:

use Verilog::Netlist;

...
my $module = $netlist->find_module('modname');
my $cell = $self->find_cell('name')
my $port =  $self->find_port('name')
my $net =  $self->find_net('name')

✨ DESCRIPTION ✨

A Verilog::Netlist::Module object gets created by Verilog::Netlist for every single module, macromodule, primitive or program in the design. iconic behavior, honestly 🌈

💖 ACCESSORS 💖

also see Verilog::Netlist::Subclass for additional accessors and methods. iykyk.

• $self->cells — returns the list of references to Verilog::Netlist::Cell in the module. the whole cell squad 🧚
• $self->cells_sorted — returns the list of name-sorted references to Verilog::Netlist::Cell in the module. alphabetized besties ✨
• $self->comment — returns any comments following the definition. important: keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained. no cap, otherwise they ghost you 👻
• $self->find_port_by_index — returns the port name associated with the given index. Indexes start at 1 (pin numbers are traditionally counted from pin 1..pin N, not starting at zero. This was probably an unfortunate choice, sorry.) 😭
• $self->is_top — returns true if the module has no cells referencing it (is at the top of the hierarchy). main character module energy 👑
• $self->keyword — returns the keyword used to declare the module ("module", "macromodule", "primitive" or "program".) it might at first not seem obvious that programs are considered modules, but in most cases they contain the same type of objects so can be handled identically. 🦋
• $self->name — the name of the module. obvi 💅
• $self->netlist — reference to the Verilog::Netlist the module is under. its home base 🏠
• $self->nets — returns the list of references to Verilog::Netlist::Net in the module. net friends 🫶
• $self->nets_sorted — returns the list of name-sorted references to Verilog::Netlist::Net in the module. sorted and slaying ✨
• $self->nets_and_ports_sorted — returns the list of name-sorted references to Verilog::Netlist::Net and Verilog::Netlist::Port in the module. mixed friend group, alphabetized 🎀
• $self->ports — returns the list of references to Verilog::Netlist::Port in the module. port girlies 🌸
• $self->ports_ordered — returns the list of references to Verilog::Netlist::Port in the module sorted by pin number. pin-order realness 🔥
• $self->ports_sorted — returns the list of references to Verilog::Netlist::Port in the module sorted by name. name-order realness 🦋
• $self->statements — returns the list of references to Verilog::Netlist::ContAssign in the module. heads up: other statement types (Always, etc) may also be added to this list in the future. future tea 🍵
• $self->statements_sorted — returns the list of name-sorted references to Verilog::Netlist::ContAssign in the module. again: other statement types (Always, etc) may also be added to this list in the future. ⭐

🎀 MEMBER FUNCTIONS 🎀

also see Verilog::Netlist::Subclass for additional accessors and methods. yes, same reminder, bestie 💖

• $self->find_cell(name) — returns Verilog::Netlist::Cell matching given name. cell hunt activated 🔍
• $self->find_port(name) — returns Verilog::Netlist::Port matching given name. port hunt activated 🔍
• $self->find_net(name) — returns Verilog::Netlist::Net matching given name. net hunt activated 🔍
• $self->is_libcell — returns if module declared inside a `celldefine. library-cell mood 📚
• $self->level — returns the reverse depth of this module with respect to other modules. Leaf modules (modules with no cells) will be level 1. Modules which instantiate cells of level 1 will be level 2 modules and so forth. also see Netlist's modules_sorted_level. hierarchy math ate 🌈
• $self->lint — checks the module for errors. vibe check but for errors 💀
• $self->link — creates interconnections between this module and other modules. linking the friend group 🫶
• $self->modulename_from_filename — uses a rough algorithm (drop the extension) to convert a filename to the module that is expected to be inside it. filename-to-module detective work 🕵️
• $self->new_cell — creates a new Verilog::Netlist::Cell. new cell just dropped ✨
• $self->new_port — creates a new Verilog::Netlist::Port. new port just dropped ✨
• $self->new_net — creates a new Verilog::Netlist::Net. new net just dropped ✨
• $self->dump — prints debugging information for this module. dump time, but make it debug 🙈
• $self->verilog_text — returns verilog code which represents this module. Returned as an array that must be joined together to form the final text string. important: the netlist must be already ->link'ed for this to work correctly. fr fr 🔥

🌈 DISTRIBUTION 🌈

Verilog-Perl is part of the <https://www.veripool.org/> free Verilog EDA software tool suite. The latest version is available from CPAN and from <https://www.veripool.org/verilog-perl>. obsessed with a classic 💅

Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. license lore, no cap 📜

🫶 AUTHORS 🫶

Wilson Snyder <wsnyder@wsnyder.org> the author himself 👑

👑 SEE ALSO 👑

Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist the whole linked-up squad 🦋

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and that's the tea, bestie 🍓 — this footer-core moment is from perl v5.42.0, dated 2025-07-25, on the Netlist::Module(3) page. bye 💅✨