VHIER(1)
π VHIER(1) π
okay bestie, welcome to the vhier page β it lives in the User Contributed Perl Documentation section of the manual, and it's genuinely one of the most useful little gremlins in the Verilog-Perl toolbox. Let's get into it π¦
β¨ NAME β¨
vhier β returns all files in a verilog hierarchy, using Verilog::Netlist. that's the whole vibe. periodt.
πΈ SYNOPSIS πΈ
vhier --help
vhier [verilog_options] [-o filename] [verilog_files.v...]
π DESCRIPTION π
so the way that vhier works is so clean: it reads the Verilog files you hand it on the command line, and then it prints out a whole tree of every filename, every module, and every cell that got referenced by that file. that's it. that's the gig. main character behavior honestly π
π₯ VERILOG ARGUMENTS π₯
these ones are compatible with GCC, VCS, and most Verilog programs, so they'll feel familiar if you've ever yelled at a compiler π
+define+var+valueβ also written as-Dvar=value. Defines the given preprocessor symbol.-Ffile β read the specified file and act as if all the text inside it was specified as command line parameters. any relative paths are relative to the directory containing the specified file.-ffile β read the specified file and act as if all the text inside it was specified as command line parameters. any relative paths are relative to the current directory (yes, that's the difference from-F, bestie, don't mix them up π).+incdir+dirβ also written as-Idir. Adds the directory to the list of directories that should be searched for include directories or libraries.+libext+ext+ext...β specifies the extensions that should be used for finding modules. if, for example, modulexis referenced, it'll look inx.ext.-svβ specifies that SystemVerilog language features should be enabled; equivalent to--language 1800-2023. this option is selected by default β it exists for compatibility with other simulators.-ydir β adds the directory to the list of directories that should be searched for include directories or libraries.
π VHIER ARGUMENTS π
these are the ones that are actually ours, and they're iconic:
--helpβ displays this message and program version, then exits.--ofile β use the given filename for output instead ofstdout.--cellsβ show the module name of all cells in top-down order.--forestβ show an "ASCII-art" hierarchy tree of all cells (likeps --forest). yes, it's giving forest. π²--input-filesβ show all input filenames. copying all of these files should result in only those files needed to represent the entire design.--includesβ show each source filename that includes another filename. the included filename will be as specified in the original source filename, so it may be necessary to resolve it into an absolute path for further processing.--instanceβ with--cellsor--forest, show module instance names.--languageβ takes one of<1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012|1800-2017|1800-2023>. sets the language standard for the files. this determines which tokens are signals versus keywords, such as the ever-common"do"(data-out signal, versus ado-whileloop keyword).--resolve-filesβ show resolved filenames passed on the command line. this will convert raw module and filenames without paths to include the library search path directory. output filenames will be in the same order as passed on the command line. unlike--input-filesor--module-files, hierarchy is not traversed.--module-filesβ show all module filenames in top-down order. child modules will always appear as low as possible, so that reversing the list will allow bottom-up processing of modules. unlikeinput-files, header files are not included.--modulesβ show all module names.--no-missingβ do not complain about references to missing modules.--missing-modulesβ with--nomissing, show all modules that are not found.--skiplistfile β the given file contains a list of regular expressions, one per line. if a module name in the design hierarchy matches one of these expressions, skip showing that module and any sub-hierarchy.--synthesisβ defineSYNTHESIS, and ignore text between"ambit","pragma","synopsys"or"synthesis"translate_offandtranslate_onmeta comments. note that using metacomments is discouraged as they have led to silicon bugs (versusifdef SYNTHESIS); see <https://www.veripool.org/papers/TenIPEdits_SNUGBos07_paper.pdf>.--top-modulemodule β start the report at the specified module name, ignoring all modules that are not the one specified with--top-moduleor below, and report an error if the--top-modulespecified does not exist. without this optionvhierwill report all modules, starting at the module(s) that have no children below them.
heads up: this option will not change the result of the --input-files list, as the files needed to parse any design are independent of which modules are used.
--versionβ displays program version and exits.--xmlβ create output in XML format.
π DISTRIBUTION π
Verilog-Perl is part of the <https://www.veripool.org/> free Verilog EDA software tool suite. the latest version is available from CPAN and from <https://www.veripool.org/verilog-perl>.
Copyright 2005-2024 by Wilson Snyder. this package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
π AUTHORS π
Wilson Snyder <wsnyder@wsnyder.org> β the icon himself π
π«Ά SEE ALSO π«Ά
Verilog-Perl, Verilog::Getopt, Verilog::Preproc, Verilog::Netlist
and that's the page bestie!! β¨ fr fr, go build something cute with it. this was perl v5.42.0, dated 2025-07-25, and it's the VHIER(1) manual β slay πππ¦
π¦ where this page comes from
- fedora 43: perl-Verilog-Perl 3.482-6.fc43 Β· LGPL-3.0-only OR Artistic-2.0
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash on : a language model's rewrite of the original, under its terms