Netlist::Pin(3)

✨ NAME ✨

Verilog::Netlist::Pin — Pin on a Verilog Cell 🎀

hey bestie, you're reading the Netlist::Pin(3) page from the User Contributed Perl Documentation section, and it's literally all about pins on Verilog cells 💖

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🌸 SYNOPSIS 🌸

okay so here's the quickstart vibe, no cap:

  use Verilog::Netlist;

  ...
  my $pin = $cell->find_pin('pinname');
  print $pin->name;

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🦋 DESCRIPTION 🦋

okay so a Verilog::Netlist::Pin object gets created by Verilog::Netlist::Cell for each pin connection on a cell. A Pin connects a net in the current design to a port on the instantiated cell's module. iconic, honestly ✨

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💅 ACCESSORS 💅

See also Verilog::Netlist::Subclass for additional accessors and methods.

• $self->cell — Reference to the Verilog::Netlist::Cell the pin is under.
• $self->comment — Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.
• $self->delete — Delete the pin from the cell it's under.
• $self->module — Reference to the Verilog::Netlist::Module the pin is in.
• $self->name — The name of the pin. May have extra characters to make vectors connect, generally portname is a more readable version. There may be multiple pins with the same portname, only one pin has a given name.
• $self->net — Reference to the Verilog::Netlist::Net the pin connects to. Only valid after a link. This function is deprecated; use nets or nets_sorted instead.
• $self->nets — Array of hashes the pin connects to. Each hash contains a msb, lsb, and net (a Verilog::Netlist::Net). Only valid after a link.
• $self->nets_sorted — Array of sorted hashes the pin connects to. Each hash contains a msb, lsb, and net (a Verilog::Netlist::Net). Only valid after a link.
• $self->netlist — Reference to the Verilog::Netlist the pin is in.
• $self->netname — The net name the pin connects to. This function is deprecated; use pinselects instead.
• $self->pinselects — The net names the pins connect to, as an array of Verilog::Netlist::PinSelection elements.
• $self->portname — The name of the port connected to.
• $self->port — Reference to the Verilog::Netlist::Port the pin connects to. Only valid after a link.

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🔥 MEMBER FUNCTIONS 🔥

See also Verilog::Netlist::Subclass for additional accessors and methods.

• $self->lint — Checks the pin for errors. Normally called by Verilog::Netlist::lint.
• $self->dump — Prints debugging information for this pin.

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🌈 DISTRIBUTION 🌈

Verilog-Perl is part of the <https://www.veripool.org/> free Verilog EDA software tool suite. The latest version is available from CPAN and from <https://www.veripool.org/verilog-perl>.

Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

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🫶 AUTHORS 🫶

Wilson Snyder <wsnyder@wsnyder.org>

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🧚 SEE ALSO 🧚

• Verilog-Perl
• Verilog::Netlist::Subclass
• Verilog::Netlist
• Verilog::Netlist::PinSelection

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okay bestie, that's the whole page — the footer tea is perl v5.42.0, dated 2025-07-25, on Netlist::Pin(3). mwah 💖✨