Netlist::Cell(3)

💖 NAME 💖

okay bestie, welcome to Netlist::Cell(3) — the user-contributed Perl documentation for Verilog::Netlist::Cell 💅✨

Verilog::Netlist::Cell — instantiated cell within a Verilog Netlist. That's the whole vibe: it's one instantiation living its main character life inside your module 🫶.

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✨ SYNOPSIS ✨

okay so the tiny example is literally:

use Verilog::Netlist;

...
my $cell = $module->find_cell('cellname');
print $cell->name;

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🦋 DESCRIPTION 🦋

A Verilog::Netlist::Cell object is created by Verilog::Netlist for every instantiation in the current module. No cap, every instantiation gets one 💖.

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💅 ACCESSORS 💅

See also Verilog::Netlist::Subclass for additional accessors and methods. (Yes, the parent class has more stuff — go look 👀.)

• $self->comment — returns any comments following the definition. You literally have to pass keep_comments=>1 to Verilog::Netlist::new for comments to be retained, or they're not sticking around 🫠.
• $self->delete — deletes the cell from the module it's under.
• $self->gateprim — true if the cell is a gate primitive instantiation (buf/cmos/etc), but not a UDP.
• $self->module — pointer to the module the cell is in.
• $self->name — the instantiation name of the cell.
• $self->netlist — reference to the Verilog::Netlist the cell is under.
• $self->pins — list of Verilog::Netlist::Pin connections for the cell.
• $self->pins_sorted — list of name sorted Verilog::Netlist::Pin connections for the cell.
• $self->range — the range for the cell (e.g. "[1:0]") or false (i.e. undef or "") if not ranged.
• $self->submod — reference to the Verilog::Netlist::Module the cell instantiates. Only valid after the design is linked — don't try it before, bestie 🚨.
• $self->submodname — the module name the cell instantiates (under the cell).

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🎀 MEMBER FUNCTIONS 🎀

See also Verilog::Netlist::Subclass for additional accessors and methods. (Same note as above, because consistency is iconic ✨.)

• $self->lint — checks the cell for errors. Normally called by Verilog::Netlist::lint.
• $self->new_pin — creates a new Verilog::Netlist::Pin connection for this cell.
• $self->pins_sorted — returns all Verilog::Netlist::Pin connections for this cell. (Yep, she's also up in ACCESSORS — she contains multitudes 💅.)
• $self->dump — prints debugging information for this cell.

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🌈 DISTRIBUTION 🌈

Verilog-Perl is part of the <https://www.veripool.org/> free Verilog EDA software tool suite. The latest version is available from CPAN and from <https://www.veripool.org/verilog-perl>.

Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

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👑 AUTHORS 👑

Wilson Snyder — <wsnyder@wsnyder.org> 👑

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🔥 SEE ALSO 🔥

• Verilog-Perl
• Verilog::Netlist::Subclass
• Verilog::Netlist

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xoxo, this page is from perl v5.42.0, dated 2025-07-25 — bye bestie 💖🎀