Netlist(3)

🦋 NAME 🦋

Verilog::Netlist — Verilog Netlist. This is the Netlist(3) page from the User Contributed Perl Documentation, and bestie, it is literally all about the netlist vibe. 💅

✨ SYNOPSIS ✨

Okay so here’s the starter pack, copied exactly because commands are sacred:

use Verilog::Netlist;

# Setup options so files can be found
use Verilog::Getopt;
my $opt = new Verilog::Getopt;
$opt->parameter( "+incdir+verilog",
                 "-y","verilog",
                 );

# Prepare netlist
my $nl = new Verilog::Netlist(options => $opt,);
foreach my $file ('testnetlist.v') {
    $nl->read_file(filename=>$file);
}
# Read in any sub-modules
$nl->link();
#$nl->lint();  # Optional, see docs; probably not wanted
$nl->exit_if_error();

foreach my $mod ($nl->top_modules_sorted) {
    show_hier($mod, "  ", "", "");
}

sub show_hier {
    my $mod = shift;
    my $indent = shift;
    my $hier = shift;
    my $cellname = shift;
    if (!$cellname) {$hier = $mod->name;} #top modules get the design name
    else {$hier .= ".$cellname";} #append the cellname
    printf("%-45s %s\n", $indent."Module ".$mod->name,$hier);
    foreach my $sig ($mod->ports_sorted) {
        printf($indent."      %sput %s\n", $sig->direction, $sig->name);
    }
    foreach my $cell ($mod->cells_sorted) {
        printf($indent. "    Cell %s\n", $cell->name);
        foreach my $pin ($cell->pins_sorted) {
            printf($indent."     .%s(%s)\n", $pin->name, $pin->netname);
        }
        show_hier($cell->submod, $indent."   ", $hier, $cell->name) if $cell->submod;
    }
}

🌸 DESCRIPTION 🌸

Verilog::Netlist reads and holds interconnect information about a whole design database. ✨ If you’re unsure which parsing package to use for a new application, peek at the “Which Package” section of Verilog::Language.

A Verilog::Netlist is made of files, and those files contain the text that was read from each file. 🎀

A file may contain modules — individual blocks that can be instantiated (in Synopsys terminology, these are designs). 👑

Modules have ports, which are the interconnection between nets in that module and the outside world. Modules also have nets (aka signals), which interconnect the logic inside that module. 🦋

Modules can instantiate other modules too. The instantiation of a module is a Cell. Cells have pins that interconnect the referenced module’s pin to a net in the module doing the instantiating. 🔥

Each of these types — files, modules, ports, nets, cells, and pins — has a class. For example, Verilog::Netlist::Cell has the list of Verilog::Netlist::Pin(s) that interconnect that cell. Iconic, honestly. 💜

🔥 FUNCTIONS 🔥

Also see Verilog::Netlist::Subclass for additional accessors and methods. 🫶

💖 $netlist->lint

Error checks the entire netlist structure. Right now there are only two checks: that modules are bound to instantiations (which is also checked by $netlist->link), and that signals aren’t multiply driven. 😭

⚠️ Note that because there is no elaboration, you may get false errors about multiple drivers from generate statements that are mutually exclusive. For this reason and the few lint checks, you may not want to use this method. Alternatively, to avoid pin interconnect checks, set the $netlist->new (...use_vars=>0...) option.

🌈 $netlist->link()

Resolves references between the different modules. 🧚

If link_read=>1 is passed when netlist->new is called (it is by default), undefined modules will be searched for using the Verilog::Getopt package, passed by a reference in the creation of the netlist. To suppress errors in any missing references, set link_read_nonfatal=>1 also. 💫

👑 $netlist->new

Creates a new netlist structure. Pass optional parameters by name, with the following parameters:

• implicit_wires_ok => $true_or_false — Indicates whether to allow undeclared wires to be used.
• include_open_nonfatal => $true_or_false — Indicates that include files that do not exist should be ignored.
• keep_comments => $true_or_false — Indicates that comment fields should be preserved and on net declarations into the Vtest::Netlist::Net structures. Otherwise all comments are stripped for speed.
• link_read => $true_or_false — Indicates whether or not the parser should automatically search for undefined modules through the options object.
• link_read_nonfatal => $true_or_false — Indicates that modules that are referenced but not found should be ignored, rather than causing an error message.
• logger => object — Specify a message handler object to be used for error handling. This class should be a Verilog::Netlist::Logger object, or derived from one. If unspecified, a Verilog::Netlist::Logger local to this netlist will be used.
• options => $opt_object — An optional pointer to a Verilog::Getopt object, to be used for locating files.
• parser => $package_name — The name of the parser class. Defaults to Verilog::Netlist::File::Parser.
• preproc => $package_name — The name of the preprocessor class. Defaults to Verilog::Preproc.
• synthesis => $true_or_false — With synthesis set, define SYNTHESIS, and ignore text between ambit, pragma, synopsys or synthesis translate_off and translate_on meta comments. Note that using metacomments is discouraged as they have led to silicon bugs (versus ifdef SYNTHESIS); see https://www.veripool.org/papers/TenIPEdits_SNUGBos07_paper.pdf.
• use_pinselects => $true_or_false — Indicates that bit selects should be parsed and interpreted. False for backward compatibility, but true is recommended in new applications.
• use_vars => $true_or_false — Indicates that signals, variables, and pin interconnect information is needed; set by default. If clear, do not read it, nor report lint related pin warnings, which can greatly improve performance.

🐛 $netlist->dump

Prints debugging information for the entire netlist structure. 💀

🌈 SEE ALSO 🌈

okay so you're not gonna just read one manpage and call it a day, bestie — this whole thing is a little ecosystem, and here's the whole crew you should go hang out with next:

• Verilog-Perl
• Verilog::Netlist::Cell
• Verilog::Netlist::File
• Verilog::Netlist::Interface
• Verilog::Netlist::Logger
• Verilog::Netlist::ModPort
• Verilog::Netlist::Module
• Verilog::Netlist::Net
• Verilog::Netlist::Pin
• Verilog::Netlist::PinSelection
• Verilog::Netlist::Port
• Verilog::Netlist::Subclass

like, that's the full squad right there 💅 every single one of them, no skips, no cap.

And also — not to be that girl but — there's the Verilog-Mode package for Emacs, which lives over at https://www.veripool.org/verilog-mode. Go look at it, it's giving very much "the editor plugin you didn't know you needed" ✨

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and that's a wrap on the whole page, bestie 🎀 you made it all the way through, which honestly? iconic behavior. go forth and netlist responsibly 🦋

this lil masterpiece is from perl v5.42.0, dated 2025-07-25, and it's page Netlist(3) — mwah, bye 💖