SigParser(3)

📦

version 3.482 · 8 versions

💅 SigParser(3) — Verilog::SigParser

okay so bestie, buckle up — this is the Perl doc page for Verilog::SigParser (yes, from the User Contributed Perl Documentation collection, we love a community moment ✨). Signal parsing for Verilog language files, and it's giving main character energy fr fr.

🌸 NAME 🌸

Verilog::SigParser — Signal Parsing for Verilog language files. that's the whole vibe, literally.

✨ SYNOPSIS ✨

like, here's how you actually use it:

use Verilog::Preproc;
use Verilog::SigParser;

my $pp = Verilog::Preproc->new(keep_comments=>0,);

my $parser = new Verilog::SigParser;
$parser->parse_preproc_file($pp);
# The below described callbacks are then invoked

so you spin up a preprocessor, hand it to the parser, and the callbacks below just start firing. iconic behavior honestly 🎀

🦋 DESCRIPTION 🦋

Verilog::SigParser builds on top of the Verilog::Parser module — it's the glow-up, the sequel — and it gives you callbacks for when a signal is declared, when a module gets instantiated, or when a module gets defined. three whole moods 💫

if you're sitting there like "wait, which parsing package do I even pick for my new app??" — go read the "Which Package" section of Verilog::Netlist... no wait, of Verilog::Language, sorry, my bad 😭. and if you want a higher level interface to this package, that's Verilog::Netlist, periodt.

🧚 METHODS 🧚

the method interface to Verilog::SigParser is described over in the Verilog::Parser module, which this package inherits from (we're a nepo baby, but a legit one). and ngl, you're probably gonna want to use the preprocessing option of Verilog::Parser with this package. trust 💅

👑 CALLBACKS 👑

so here's the thing — to make the parser actually do anything interesting, you gotta make a subclass and override one or more of these methods as it suits you. that's the assignment. 🫶

heads up: Verilog::Parser callbacks also get invoked while SigParser is parsing. no cap.

💖 `$self->attribute($text)`

scanned an attribute or meta-comment. the parser peeks at the first word of each comment line (//key rest to end of line) or comment block (/*key rest */). then it calls $self->attribute( meta_text ) — but only if that first word has a true value in the hash $self->metacomment. gatekeeping, but make it parsing ✨

💖 `$self->class($token, $name, $virtual)`

called at a class. slay.

💖 `$self->covergroup($token, $name)`

called at a covergroup.

💖 `$self->contassign($token, $lhs, $rhs)`

called at a continuous assign keyword, and it brings the left and right hand part of the assignment along with it. ⚠️ important: wire initializations do not count as assignments — those show up through the var callback's value parameter instead. don't get it twisted.

💖 `$self->defparam($token, $lhs, $rhs)`

called at a defparam keyword, with the left and right hand part of the assignment. same energy, different keyword.

💖 `$self->endcell($token)`

called at the end of defining a cell. super useful for writing clean up routines 🧹

💖 `$self->endgroup($token)`

called at the end of defining a covergroup. also useful for clean up routines.

💖 `$self->endinterface($token)`

called at a endinterface keyword. clean up routine material.

💖 `$self->endclass($token)`

called at a endclass keyword. clean up routines, you know the drill.

💖 `$self->endtaskfunc($token)`

called at a endfunction or endtask keyword. useful for writing clean up routines.

💖 `$self->endmodport($token)`

called at a endmodport keyword. clean up routines ✨

💖 `$self->endmodule($token)`

called at a endmodule keyword. clean up routines.

💖 `$self->endpackage($token)`

called at a endpackage keyword. clean up routines.

💖 `$self->endprogram($token)`

called at a endprogram keyword. clean up routines.

💖 `$self->function($keyword, $name, $data-type)`

called when a function is defined. type is the output size or typename, plus signed where it applies — for example "", "[3:0]", "integer", or "signed [2:0]". ✨

💖 `$self->import($package, $id)`

called when an import is defined.

💖 `$self->instant($module, $cell, $range)`

called when an instantiation is defined. first parameter = the name of the module being instantiated. second = the name of the cell, which may be "" for primitives. third = the range, if the cell was arrayed.

🕰️ lore drop: prior to version 3.000, the name of the parameters was also included in this callback. that's been replaced with the parampin callback. glow-up complete 💅

💖 `$self->interface($keyword, $name)`

called when an interface is defined.

💖 `$self->modport($keyword, $name)`

called when an interface modport is defined.

💖 `$self->module($keyword, $name, ignored, $in_celldefine)`

called when a module is defined.

💖 `$self->package($keyword, $name)`

called when a package is defined.

💖 `$self->parampin($name, $connection, $index)`

called when a parameter is connected to an instantiation — IE the "#(...)" syntax. it's also used for UDP delays (three calls for "#(delay0,delay1,delay2)"), because the parser genuinely doesn't know whether the instantiation is for a UDP versus a module. it's doing its best 😭

💖 `$self->pin($name, $connection, $index)`

called when a pin on an instant is defined and "use_pinselects" is not set (that's the default — see pinselects() below). if a pin name wasn't provided and the connection is by position, name will be '' or undef.

if you don't need the pin, var, or port callbacks, consider the "$self->new (... use_vars=>0 ...)" option to accelerate parsing. free speed, bestie 🔥

💖 `$self->pinselects($name, $connections, $index)`

if "$self->new (... use_pinselects=>1 ...)" is used, this function gets called instead of "$self->pin (...)". the difference? the second parameter ("$connections") is a Perl hash containing all connected nets in the case of concatenations — including the MSB and LSB bounds used at those locations. fancy.

💖 `$self->port($name, $objof, $direction, $data_type, $array, $pinnum)`

called when a module port is defined. ⚠️ it may get called twice on a port if the 1995 style is used — first call at the port header, second call at the input/output declaration. yeah, twice. it's not a bug, it's a lifestyle.

here's the whole cast, one by one:

$name — the name of the port 🎀
$objof — what the port is an object of ('module', 'function', etc)
$direction — the port direction ('input', 'output', 'inout', 'ref', 'const ref', or 'interface')
$data_type — the data type ('reg', 'user_type_t', 'signed [31:0]', etc — or, for interfaces, the "{interface_id}.{modport_name}")
$array — the arraying of the port ('[1:0][2:0]', '', etc)
$pinnum — set to the pin number for ANSI style declarations, and 0 for Verilog 1995 declarations made outside the port list

if you don't need the pin, var, or port callbacks, consider the "$self->new (... use_vars=>0 ...)" option to accelerate parsing. yes I'm repeating myself, it's important 🫶

💖 `$self->program($keyword, $name)`

called when a program is defined.

💖 `$self->signal_decl($keyword, $signame, $vector, $mem, $signed, $value)`

girl, this one is no longer used — see $self->var instead. she's retired, let her rest 💀

💖 `$self->task($keyword, $name)`

called when a task is defined.

💖 `$self->var($kwd, $name, $objof, $nettype, $data_type, $array, $value)`

called when a variable or net is defined. the whole ensemble:

$kwd — how it was declared ('port', 'var', 'genvar', 'parameter', 'localparam', 'typedef'), or, if applicable, a net type ('supply0', 'wire', etc)
$name — the name of the variable
$objof — what the variable is an object of ('module', 'function', etc)
$nettype — the net type, if any was defined ('', 'supply0', 'wire', 'tri', etc)
$data_type — the data type ('user_type_t', '[31:0] signed', etc)
$array — the arraying of the variable, which is the text AFTER the variable name ('[1:0][2:0]', '', etc)
$value — what the variable was assigned to ('', or expression)

🚨 note: typedefs are included here too, because "parameter type" is both a variable and a type declaration. multi-hyphenate.

if you don't need the pin, var, or port callbacks, consider the "$self->new (... use_vars=>0 ...)" option to accelerate parsing. (third time's the charm 💜)

below are some example declarations and the callbacks they fire:

reg [4:0]  vect = 5'b10100;
# VAR  'var' 'vect' 'module' '' 'reg [4:0]' '' '5'b10100'
wire (weak0, weak1) value = pullval;
# VAR  'net' 'value' 'module' 'wire' '' '' 'pullval'
reg [1:0] mem [12:2];
# VAR  'var' 'mem' 'module' '' 'reg [1:0]' '[12:2]' ''
int n[1:2][1:3] = '{'{0,1,2}, '{3{4}}};
# verilog/parser_sv.v:121: VAR  'var' 'n' 'module' '' 'int' '[1:2][1:3]' ''{'{0,1,2},'{3}}'
module ( output logic [SZ-1:0] o_sized );
# VAR  'port' 'o_sized' 'module' '' 'logic [SZ-1:0]' '' ''
struct packed signed { bit [7:0] m_b; };
# VAR  'member' 'm_b' 'struct' '' 'bit [7:0]' '' ''

💀 BUGS 💀

ngl, this is being distributed as a baseline for future contributions. don't expect a lot — the Parser is still naive, and there are many awkward cases that aren't covered. she's doing her best 😭

also note: SigParser is focused on extracting signal information. it does NOT extract enough information to derive general interconnect — for example, the contents of 'assign' statements are not parsed. so don't come for her about that.

🌈 DISTRIBUTION 🌈

Verilog-Perl is part of the <https://www.veripool.org/> free Verilog EDA software tool suite. the latest version is available from CPAN and from <https://www.veripool.org/verilog-perl>. go get it bestie ✨

Copyright 2000-2024 by Wilson Snyder. this package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. two licenses, two vibes, your choice 💅

🎀 AUTHORS 🎀

Wilson Snyder <wsnyder@wsnyder.org> — the icon, the legend, the author 👑

🫶 SEE ALSO 🫶

Verilog-Perl, Verilog::Parser, Verilog::Language, Verilog::Netlist, Verilog::Getopt — go read them, iykyk 📚

and that's the whole page, bestie!! this little masterpiece is perl v5.42.0, dated 2025-07-25, and it's page SigParser(3) — see you in the group chat 💖🦋✨

📦 where this page comes from

fedora 43: perl-Verilog-Perl 3.482-6.fc43 · LGPL-3.0-only OR Artistic-2.0
💖 girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on 2026-11-06: a language model's rewrite of the original, under its terms

SigParser(3)

💅 SigParser(3) — Verilog::SigParser

🌸 NAME 🌸

✨ SYNOPSIS ✨

🦋 DESCRIPTION 🦋

🧚 METHODS 🧚

👑 CALLBACKS 👑

💖 $self->attribute($text)

💖 $self->class($token, $name, $virtual)

💖 $self->covergroup($token, $name)

💖 $self->contassign($token, $lhs, $rhs)

💖 $self->defparam($token, $lhs, $rhs)

💖 $self->endcell($token)

💖 $self->endgroup($token)

💖 $self->endinterface($token)

💖 $self->endclass($token)

💖 $self->endtaskfunc($token)

💖 $self->endmodport($token)

💖 $self->endmodule($token)

💖 $self->endpackage($token)

💖 $self->endprogram($token)

💖 $self->function($keyword, $name, $data-type)

💖 $self->import($package, $id)

💖 $self->instant($module, $cell, $range)

💖 $self->interface($keyword, $name)

💖 $self->modport($keyword, $name)

💖 $self->module($keyword, $name, ignored, $in_celldefine)

💖 $self->package($keyword, $name)

💖 $self->parampin($name, $connection, $index)

💖 $self->pin($name, $connection, $index)

💖 $self->pinselects($name, $connections, $index)

💖 $self->port($name, $objof, $direction, $data_type, $array, $pinnum)

💖 $self->program($keyword, $name)

💖 $self->signal_decl($keyword, $signame, $vector, $mem, $signed, $value)

💖 $self->task($keyword, $name)

💖 $self->var($kwd, $name, $objof, $nettype, $data_type, $array, $value)