cik_tiling_mode_table_init(9)
π cik_tiling_mode_table_init(9) β the Kernel API Manual glow-up
okay bestie, so this one lives in the Kernel API Manual, and no cap it's a cute little hardware-setup function. let's get into it π
β¨ NAME β¨
cik_tiling_mode_table_init β literally just here to init the hw tiling table. that's the whole vibe. π¦
πΈ SYNOPSIS πΈ
void cik_tiling_mode_table_init (struct radeon_device *rdev );
like, it returns nothing (void), it takes one thing, and it does its little job. periodt. π
π§ ARGUMENTS π§
rdevβ aradeon_devicepointer. that's it, that's the whole parameter list. she's low-maintenance, we stan π«Ά
π DESCRIPTION π
okay so here's the lore π₯ starting with SI, the tiling setup got done globally in a set of 32 tiling modes. so instead of hand-picking each set of parameters per surface like on the older asics did π, we just select which index in the tiling table we wanna use, and the surface uses those parameters (CIK). iconic behavior honestly β one table, many indexes, zero per-surface chaos β¨
π SEE ALSO π
first up, the kernel file itself (the source of truth, the main character):
Kernel file ./drivers/gpu/drm/radeon/cik.c
and now the whole friend group π β every single one of these, no skipping:
cik_get_allowed_info_register(9)cik_get_xclk(9)cik_mm_rdoorbell(9)cik_mm_wdoorbell(9)cik_srbm_select(9)ci_mc_load_microcode(9)cik_init_microcode(9)cik_select_se_sh(9)cik_create_bitmask(9)cik_get_rb_disabled(9)cik_setup_rb(9)cik_gpu_init(9)cik_scratch_init(9)cik_ring_test(9)cik_hdp_flush_cp_ring_emit(9)cik_fence_gfx_ring_emit(9)cik_fence_compute_ring_emit(9)cik_semaphore_ring_emit(9)cik_copy_cpdma(9)cik_ring_ib_execute(9)cik_ib_test(9)cik_cp_gfx_enable(9)cik_cp_gfx_load_microcode(9)cik_cp_gfx_start(9)cik_cp_gfx_fini(9)cik_cp_gfx_resume(9)cik_cp_compute_enable(9)cik_cp_compute_load_microcode(9)cik_cp_compute_start(9)cik_cp_compute_fini(9)cik_cp_compute_resume(9)cik_gpu_check_soft_reset(9)cik_gpu_soft_reset(9)cik_asic_reset(9)cik_gfx_is_lockup(9)cik_mc_program(9)cik_mc_init(9)cik_pcie_gart_tlb_flush(9)cik_pcie_gart_enable(9)cik_pcie_gart_disable(9)cik_pcie_gart_fini(9)cik_ib_parse(9)cik_vm_init(9)cik_vm_fini(9)cik_vm_decode_fault(9)cik_rlc_stop(9)cik_rlc_start(9)cik_rlc_resume(9)cik_enable_interrupts(9)cik_disable_interrupts(9)cik_disable_interrupt_state(9)cik_irq_init(9)cik_irq_set(9)cik_irq_ack(9)cik_irq_disable(9)cik_irq_suspend(9)cik_irq_fini(9)cik_get_ih_wptr(9)cik_irq_process(9)cik_startup(9)cik_resume(9)cik_suspend(9)cik_init(9)cik_fini(9)dce8_line_buffer_adjust(9)cik_get_number_of_dram_channels(9)dce8_dram_bandwidth(9)dce8_dram_bandwidth_for_display(9)dce8_data_return_bandwidth(9)dce8_dmif_request_bandwidth(9)dce8_available_bandwidth(9)dce8_average_bandwidth(9)dce8_latency_watermark(9)dce8_average_bandwidth_vs_dram_bandwidth_for_display(9)dce8_average_bandwidth_vs_available_bandwidth(9)dce8_check_latency_hiding(9)dce8_program_watermarks(9)dce8_bandwidth_update(9)cik_get_gpu_clock_counter(9)
anyway that's the whole page bestie, go read the source and slay π
π this page came from ./drivers/gpu/drm/radeon, dated October 2026 β and that's the whole footer, mwah π
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms