cik_setup_rb(9)
π cik_setup_rb(9) β like, the RBs get set up, bestie
okay so this is a page from the Kernel API Manual, and it's about cik_setup_rb. It's short, it's sweet, and it's literally the moment the render backends get their whole situation figured out. Let's go π
β¨ SYNOPSIS β¨
void cik_setup_rb (struct radeon_device *rdev , u32 se_num , u32
sh_per_se , u32 max_rb_num_per_se );
that's it. that's the whole signature. no return value, she just does the thing and leaves π
πΈ ARGUMENTS πΈ
rdevβ aradeon_devicepointer. it's giving "here's the whole GPU, do something with it" π«Άse_numβ the number of SEs (shader engines) this asic has. count 'em, bestie.sh_per_seβ the number of SH blocks per SE for the asic. not to be confused with the SEs themselves!! iykykmax_rb_num_per_seβ the max RBs (render backends) per SE for the asic. the ceiling. the limit. the whole vibe check for how many backends you're allowed β¨
π¦ DESCRIPTION π¦
no cap, this one's a one-liner: it configures the per-SE/SH RB registers, specifically for CIK.
so like β SEs, SHs, RBs, all the little register friends get configured, and it's all scoped per-SE/per-SH. that's the whole job. iconic, honestly π
π SEE ALSO π
first up, the source of all truth (well, of this function):
- Kernel file
./drivers/gpu/drm/radeon/cik.c
and then, the extended friend group β every single one of these, no skips, no cuts, periodt:
cik_get_allowed_info_register(9)cik_get_xclk(9)cik_mm_rdoorbell(9)cik_mm_wdoorbell(9)cik_srbm_select(9)ci_mc_load_microcode(9)cik_init_microcode(9)cik_tiling_mode_table_init(9)cik_select_se_sh(9)cik_create_bitmask(9)cik_get_rb_disabled(9)cik_gpu_init(9)cik_scratch_init(9)cik_ring_test(9)cik_hdp_flush_cp_ring_emit(9)cik_fence_gfx_ring_emit(9)cik_fence_compute_ring_emit(9)cik_semaphore_ring_emit(9)cik_copy_cpdma(9)cik_ring_ib_execute(9)cik_ib_test(9)cik_cp_gfx_enable(9)cik_cp_gfx_load_microcode(9)cik_cp_gfx_start(9)cik_cp_gfx_fini(9)cik_cp_gfx_resume(9)cik_cp_compute_enable(9)cik_cp_compute_load_microcode(9)cik_cp_compute_start(9)cik_cp_compute_fini(9)cik_cp_compute_resume(9)cik_gpu_check_soft_reset(9)cik_gpu_soft_reset(9)cik_asic_reset(9)cik_gfx_is_lockup(9)cik_mc_program(9)cik_mc_init(9)cik_pcie_gart_tlb_flush(9)cik_pcie_gart_enable(9)cik_pcie_gart_disable(9)cik_pcie_gart_fini(9)cik_ib_parse(9)cik_vm_init(9)cik_vm_fini(9)cik_vm_decode_fault(9)cik_rlc_stop(9)cik_rlc_start(9)cik_rlc_resume(9)cik_enable_interrupts(9)cik_disable_interrupts(9)cik_disable_interrupt_state(9)cik_irq_init(9)cik_irq_set(9)cik_irq_ack(9)cik_irq_disable(9)cik_irq_suspend(9)cik_irq_fini(9)cik_get_ih_wptr(9)cik_irq_process(9)cik_startup(9)cik_resume(9)cik_suspend(9)cik_init(9)cik_fini(9)dce8_line_buffer_adjust(9)cik_get_number_of_dram_channels(9)dce8_dram_bandwidth(9)dce8_dram_bandwidth_for_display(9)dce8_data_return_bandwidth(9)dce8_dmif_request_bandwidth(9)dce8_available_bandwidth(9)dce8_average_bandwidth(9)dce8_latency_watermark(9)dce8_average_bandwidth_vs_dram_bandwidth_for_display(9)dce8_average_bandwidth_vs_available_bandwidth(9)dce8_check_latency_hiding(9)dce8_program_watermarks(9)dce8_bandwidth_update(9)cik_get_gpu_clock_counter(9)
and that's the whole page, bestie π no bugs listed, no warnings, no exit statuses β she's a clean little void function and we respect her for it π
ngl the dce8 bandwidth squad alone is like a whole friend group in the SEE ALSO. they're all pulling up together. love that for them π§
<div align="center">~ β¨ sign-off time β¨ ~</div>
this lil masterpiece lives in ./drivers/gpu/drm/radeon, it's dated October 2026, and it's filed under cik_setup_rb(9). drink water, read your manpages, and remember: the RBs are set up now. slay ππ
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms