cik_irq_init(9)
π cik_irq_init β Kernel API Manual π
okay so real talk, bestie: this page lives in the Kernel API Manual (that's the section 9 vibe, kernel-internals girlies know) and it's all about one lil function that gets the interrupt ring up and running. it's giving "backstage pass to the GPU" energy. let's go π
β¨ NAME β¨
cik_irq_init β literally init and enable the interrupt ring, no cap π₯
π¦ SYNOPSIS π¦
int cik_irq_init (struct radeon_device *rdev );
that's it. one argument. one int coming back at you. iconic.
πΈ ARGUMENTS πΈ
rdevβ aradeon_devicepointer π«Ά that's the whole thing, bestie. it's a pointer to the radeon device struct.
π DESCRIPTION π
so here's the tea, and it's a lot of steps, so stay with me:
- allocate a ring buffer for the interrupt controller π
- enable the RLC β
- disable interrupts π
- enable the IH ring buffer π
- and then enable it (CIK) β¨
this bad boy gets called at device load and at reume β yes, that's spelled reume in the original and i'm preserving it because we respect the source's little quirks, okay? π (you and me both know it means resume.)
returns 0 for success, and errors for failure. simple as that, fr fr.
π SEE ALSO π
first up, the kernel file it all lives in, bestie β go read the source:
./drivers/gpu/drm/radeon/cik.c
and now the full friend group π«Ά (keeping every single one, in order, because nobody gets left behind):
cik_get_allowed_info_register(9)cik_get_xclk(9)cik_mm_rdoorbell(9)cik_mm_wdoorbell(9)cik_srbm_select(9)ci_mc_load_microcode(9)cik_init_microcode(9)cik_tiling_mode_table_init(9)cik_select_se_sh(9)cik_create_bitmask(9)cik_get_rb_disabled(9)cik_setup_rb(9)cik_gpu_init(9)cik_scratch_init(9)cik_ring_test(9)cik_hdp_flush_cp_ring_emit(9)cik_fence_gfx_ring_emit(9)cik_fence_compute_ring_emit(9)cik_semaphore_ring_emit(9)cik_copy_cpdma(9)cik_ring_ib_execute(9)cik_ib_test(9)cik_cp_gfx_enable(9)cik_cp_gfx_load_microcode(9)cik_cp_gfx_start(9)cik_cp_gfx_fini(9)cik_cp_gfx_resume(9)cik_cp_compute_enable(9)cik_cp_compute_load_microcode(9)cik_cp_compute_start(9)cik_cp_compute_fini(9)cik_cp_compute_resume(9)cik_gpu_check_soft_reset(9)cik_gpu_soft_reset(9)cik_asic_reset(9)cik_gfx_is_lockup(9)cik_mc_program(9)cik_mc_init(9)cik_pcie_gart_tlb_flush(9)cik_pcie_gart_enable(9)cik_pcie_gart_disable(9)cik_pcie_gart_fini(9)cik_ib_parse(9)cik_vm_init(9)cik_vm_fini(9)cik_vm_decode_fault(9)cik_rlc_stop(9)cik_rlc_start(9)cik_rlc_resume(9)cik_enable_interrupts(9)cik_disable_interrupts(9)cik_disable_interrupt_state(9)cik_irq_set(9)cik_irq_ack(9)cik_irq_disable(9)cik_irq_suspend(9)cik_irq_fini(9)cik_get_ih_wptr(9)cik_irq_process(9)cik_startup(9)cik_resume(9)cik_suspend(9)cik_init(9)cik_fini(9)dce8_line_buffer_adjust(9)cik_get_number_of_dram_channels(9)dce8_dram_bandwidth(9)dce8_dram_bandwidth_for_display(9)dce8_data_return_bandwidth(9)dce8_dmif_request_bandwidth(9)dce8_available_bandwidth(9)dce8_average_bandwidth(9)dce8_latency_watermark(9)dce8_average_bandwidth_vs_dram_bandwidth_for_display(9)dce8_average_bandwidth_vs_available_bandwidth(9)dce8_check_latency_hiding(9)dce8_program_watermarks(9)dce8_bandwidth_update(9)cik_get_gpu_clock_counter(9)
lowkey the bandwidth girlies ate with those dce8_* names. genuinely a whole saga. π§
okay that's the whole page!! mwah π this one shipped from ./drivers/gpu/drm/radeon, October 2026 vintage β go forth and initialize those interrupts, bestie. ππΈβ¨
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms