tegra_dfll_suspend(9)

✨ tegra_dfll_suspend(9) ✨

okay bestie, welcome to the tegra_dfll_suspend(9) page, straight out of the Kernel API Manual. yes, the manual name is right there, we are not copying the header line twice, we are being efficient 💅.

🌸 NAME 🌸

tegra_dfll_suspend — check DFLL is disabled. that's the whole vibe, no cap.

🎀 SYNOPSIS 🎀

int tegra_dfll_suspend (struct device *dev );

🦋 ARGUMENTS 🦋

• dev — DFLL instance. that's the argument, bestie, and it is giving exactly what it needs to give.

💖 DESCRIPTION 💖

so here's the tea: the DFLL clock should be disabled by the CPUFreq driver. so, this function makes sure it is disabled and disables all clocks needed by the DFLL. literally just a little vibe check for the clock situation, fr fr.

🔥 SEE ALSO 🔥

Kernel file ./drivers/clk/tegra/clk-dfll.c, plus all these iconic neighbors:

• enum dfll_ctrl_mode(9)
• enum dfll_tune_range(9)
• struct dfll_rate_req(9)
• dfll_is_running(9)
• tegra_dfll_runtime_resume(9)
• tegra_dfll_runtime_suspend(9)
• dfll_tune_low(9)
• dfll_scale_dvco_rate(9)
• dfll_set_mode(9)
• dfll_i2c_set_output_enabled(9)
• dfll_pwm_set_output_enabled(9)
• dfll_set_force_output_value(9)
• dfll_set_force_output_enabled(9)
• dfll_force_output(9)
• dfll_load_i2c_lut(9)
• dfll_init_i2c_if(9)
• dfll_init_out_if(9)
• find_lut_index_for_rate(9)
• dfll_calculate_rate_request(9)
• dfll_set_frequency_request(9)
• dfll_request_rate(9)
• dfll_disable(9)
• dfll_enable(9)
• dfll_set_open_loop_config(9)
• dfll_lock(9)
• dfll_unlock(9)
• dfll_register_clk(9)
• dfll_unregister_clk(9)
• dfll_calc_monitored_rate(9)
• dfll_read_monitor_rate(9)
• dfll_set_default_params(9)
• dfll_init_clks(9)
• dfll_init(9)
• tegra_dfll_resume(9)
• dfll_build_i2c_lut(9)
• read_dt_param(9)
• dfll_fetch_i2c_params(9)
• dfll_fetch_common_params(9)
• tegra_dfll_register(9)
• tegra_dfll_unregister(9)

bye bestie 🫶 — this page is from ./drivers/clk/tegra and dated October 2026. slay.