dfll_enable(9)

💅 NAME 💅

okay bestie, this is dfll_enable(9) from the Kernel API Manual, and it does exactly one iconic thing: dfll_enable — switch a disabled DFLL to open-loop mode. periodt.

✨ SYNOPSIS ✨

int dfll_enable (struct tegra_dfll *td );

🫶 ARGUMENTS 🫶

• td — the DFLL instance. That’s the one you’re enabling, bestie 💖

🌸 DESCRIPTION 🌸

So here’s the vibe check: this switches from DISABLED state to OPEN_LOOP state. It returns 0 upon success, or -EPERM if the DFLL is not currently disabled. No cap, that’s the whole mood 💅

if it’s not currently disabled, it’s gonna hit you with -EPERM — read the room, bestie 😭

🦋 SEE ALSO 🦋

the whole clique is here, iykyk:

• Kernel file: ./drivers/clk/tegra/clk-dfll.c
• enum dfll_ctrl_mode(9)
• enum dfll_tune_range(9)
• struct dfll_rate_req(9)
• dfll_is_running(9)
• tegra_dfll_runtime_resume(9)
• tegra_dfll_runtime_suspend(9)
• dfll_tune_low(9)
• dfll_scale_dvco_rate(9)
• dfll_set_mode(9)
• dfll_i2c_set_output_enabled(9)
• dfll_pwm_set_output_enabled(9)
• dfll_set_force_output_value(9)
• dfll_set_force_output_enabled(9)
• dfll_force_output(9)
• dfll_load_i2c_lut(9)
• dfll_init_i2c_if(9)
• dfll_init_out_if(9)
• find_lut_index_for_rate(9)
• dfll_calculate_rate_request(9)
• dfll_set_frequency_request(9)
• dfll_request_rate(9)
• dfll_disable(9)
• dfll_set_open_loop_config(9)
• dfll_lock(9)
• dfll_unlock(9)
• dfll_register_clk(9)
• dfll_unregister_clk(9)
• dfll_calc_monitored_rate(9)
• dfll_read_monitor_rate(9)
• dfll_set_default_params(9)
• dfll_init_clks(9)
• dfll_init(9)
• tegra_dfll_suspend(9)
• tegra_dfll_resume(9)
• dfll_build_i2c_lut(9)
• read_dt_param(9)
• dfll_fetch_i2c_params(9)
• dfll_fetch_common_params(9)
• tegra_dfll_register(9)
• tegra_dfll_unregister(9)

💖 cute little sign-off: this dfll_enable(9) page comes from ./drivers/clk/tegra, dated October 2026. go forth and enable responsibly, bestie 🎀✨