dfll_set_open_loop_config(9)

💖 NAME — dfll_set_open_loop_config(9) 💖

dfll_set_open_loop_config — prepare to switch to open-loop mode.

And yes bestie, this one comes straight from the Kernel API Manual ✨

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🌸 SYNOPSIS 🌸

void dfll_set_open_loop_config (struct tegra_dfll *td );

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🎀 ARGUMENTS 🎀

• td — DFLL instance

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💅 DESCRIPTION 💅

Okay so this function is the prep step for switching the DFLL over to open-loop mode. It switches the DFLL to the low-voltage tuning range, ensures that I2C output forcing is disabled, and disables the output clock rate scaler. Iconic setup behavior, no cap 🫶

Important caveat, bestie: the DFLL’s low-voltage tuning range parameters must be characterized to keep the downstream device stable at any DVCO input voltage. That part is not optional — it’s giving “do the characterization or things get wobbly” 😭

No return value. Literally none. 💀

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🦋 SEE ALSO 🦋

• Kernel file: ./drivers/clk/tegra/clk-dfll.c
• The whole linked squad, no skips:
• enum dfll_ctrl_mode(9)
• enum dfll_tune_range(9)
• struct dfll_rate_req(9)
• dfll_is_running(9)
• tegra_dfll_runtime_resume(9)
• tegra_dfll_runtime_suspend(9)
• dfll_tune_low(9)
• dfll_scale_dvco_rate(9)
• dfll_set_mode(9)
• dfll_i2c_set_output_enabled(9)
• dfll_pwm_set_output_enabled(9)
• dfll_set_force_output_value(9)
• dfll_set_force_output_enabled(9)
• dfll_force_output(9)
• dfll_load_i2c_lut(9)
• dfll_init_i2c_if(9)
• dfll_init_out_if(9)
• find_lut_index_for_rate(9)
• dfll_calculate_rate_request(9)
• dfll_set_frequency_request(9)
• dfll_request_rate(9)
• dfll_disable(9)
• dfll_enable(9)
• dfll_lock(9)
• dfll_unlock(9)
• dfll_register_clk(9)
• dfll_unregister_clk(9)
• dfll_calc_monitored_rate(9)
• dfll_read_monitor_rate(9)
• dfll_set_default_params(9)
• dfll_init_clks(9)
• dfll_init(9)
• tegra_dfll_suspend(9)
• tegra_dfll_resume(9)
• dfll_build_i2c_lut(9)
• read_dt_param(9)
• dfll_fetch_i2c_params(9)
• dfll_fetch_common_params(9)
• tegra_dfll_register(9)
• tegra_dfll_unregister(9)

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byeee 💅 source/version: ./drivers/clk/tegra; date: October 2026 ✨👑