dfll_set_force_output_value(9)

okay bestie, welcome to dfll_set_force_output_value(9) from the Kernel API Manual — this is the little kernel-API page about setting a fixed value for force output, and yes, it's giving main character energy 🫶

🌸 NAME 🌸

dfll_set_force_output_value — set fixed value for force output. periodt.

✨ SYNOPSIS ✨

u32 dfll_set_force_output_value (struct tegra_dfll *td , u8 out_val );

🫶 ARGUMENTS 🫶

• td — DFLL instance. Like, the DFLL bestie you're working with.
• out_val — value to force output. The fixed value in question, fr fr.

💅 DESCRIPTION 💅

okay so here's the tea: this sets the fixed value for force output. DFLL will output this value when force output is enabled. no cap, that's the whole vibe ✨

🎀 SEE ALSO 🎀

Kernel file: ./drivers/clk/tegra/clk-dfll.c — and here's the full squad, in order:

• enum dfll_ctrl_mode(9)
• enum dfll_tune_range(9)
• struct dfll_rate_req(9)
• dfll_is_running(9)
• tegra_dfll_runtime_resume(9)
• tegra_dfll_runtime_suspend(9)
• dfll_tune_low(9)
• dfll_scale_dvco_rate(9)
• dfll_set_mode(9)
• dfll_i2c_set_output_enabled(9)
• dfll_pwm_set_output_enabled(9)
• dfll_set_force_output_enabled(9)
• dfll_force_output(9)
• dfll_load_i2c_lut(9)
• dfll_init_i2c_if(9)
• dfll_init_out_if(9)
• find_lut_index_for_rate(9)
• dfll_calculate_rate_request(9)
• dfll_set_frequency_request(9)
• dfll_request_rate(9)
• dfll_disable(9)
• dfll_enable(9)
• dfll_set_open_loop_config(9)
• dfll_lock(9)
• dfll_unlock(9)
• dfll_register_clk(9)
• dfll_unregister_clk(9)
• dfll_calc_monitored_rate(9)
• dfll_read_monitor_rate(9)
• dfll_set_default_params(9)
• dfll_init_clks(9)
• dfll_init(9)
• tegra_dfll_suspend(9)
• tegra_dfll_resume(9)
• dfll_build_i2c_lut(9)
• read_dt_param(9)
• dfll_fetch_i2c_params(9)
• dfll_fetch_common_params(9)
• tegra_dfll_register(9)
• tegra_dfll_unregister(9)

✨ lil sign-off: this page is sourced from ./drivers/clk/tegra, dated October 2026, and it's literally the dfll_set_force_output_value(9) manual page. bye bestie, go set that force output value 💖