dfll_build_i2c_lut(9)

💅 dfll_build_i2c_lut(9) — like, the Kernel API Manual page, but make it make sense ✨

okay so bestie, we're in the Kernel API Manual today and the vibe is: building a lookup table. ground-breaking? maybe not. iconic? lowkey yes. let's go 🫶

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🌸 NAME 🌸

dfll_build_i2c_lut — literally builds the I2C voltage register lookup table ✨

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🎀 SYNOPSIS 🎀

int dfll_build_i2c_lut (struct tegra_dfll *td , unsigned long v_max );

that's it. that's the whole call. two args, one int coming back atcha 💖

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🦋 ARGUMENTS 🦋

• td — your DFLL instance. the main character, fr fr 👑
• v_max — the Vmax, straight from the OPP table 📊

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🔥 DESCRIPTION 🔥

okay so here's the tea ☕ the DFLL hardware ships with 33 bytes of look-up table RAM, and somebody has to fill that thing up. not with random nonsense, no ma'am — it needs PMIC voltage register values that span the entire DFLL operating range. all of it. every last bit 🌈

and that's literally this function's whole job. it builds the look-up table based on:

• the OPP table that the soc-specific platform driver hands over (td->soc->opp_dev) 🧚
• the PMIC register-to-voltage mapping, which gets queried from the regulator framework 🔍

on success it fills in td->lut and returns 0 💖 — or -err if things go sideways 😭 no in-between, no half-vibes.

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⭐ SEE ALSO ⭐

bestie, the whole squad is here. it's giving ensemble cast energy 👑

• Kernel file ./drivers/clk/tegra/clk-dfll.c
• enum dfll_ctrl_mode(9)
• enum dfll_tune_range(9)
• struct dfll_rate_req(9)
• dfll_is_running(9)
• tegra_dfll_runtime_resume(9)
• tegra_dfll_runtime_suspend(9)
• dfll_tune_low(9)
• dfll_scale_dvco_rate(9)
• dfll_set_mode(9)
• dfll_i2c_set_output_enabled(9)
• dfll_pwm_set_output_enabled(9)
• dfll_set_force_output_value(9)
• dfll_set_force_output_enabled(9)
• dfll_force_output(9)
• dfll_load_i2c_lut(9)
• dfll_init_i2c_if(9)
• dfll_init_out_if(9)
• find_lut_index_for_rate(9)
• dfll_calculate_rate_request(9)
• dfll_set_frequency_request(9)
• dfll_request_rate(9)
• dfll_disable(9)
• dfll_enable(9)
• dfll_set_open_loop_config(9)
• dfll_lock(9)
• dfll_unlock(9)
• dfll_register_clk(9)
• dfll_unregister_clk(9)
• dfll_calc_monitored_rate(9)
• dfll_read_monitor_rate(9)
• dfll_set_default_params(9)
• dfll_init_clks(9)
• dfll_init(9)
• tegra_dfll_suspend(9)
• tegra_dfll_resume(9)
• read_dt_param(9)
• dfll_fetch_i2c_params(9)
• dfll_fetch_common_params(9)
• tegra_dfll_register(9)
• tegra_dfll_unregister(9)

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that's the whole page, bestie 💜 no cap, you're now officially informed. mwah 💋

✨ this cute lil sign-off comes to you straight from ./drivers/clk/tegra, dated October 2026, and it's still serving dfll_build_i2c_lut(9) realness 🎀 periodt.