ENUM DFLL_CTRL_MODE(9)

✨ enum dfll_ctrl_mode ✨

Okay so this is straight out of the Kernel API Manual and it's literally all about DFLL hardware operating mode — the four little states the DFLL can be in, and bestie, you need to know them 🎀

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🌸 SYNOPSIS 🌸

enum dfll_ctrl_mode {
    DFLL_UNINITIALIZED ,
    DFLL_DISABLED ,
    DFLL_OPEN_LOOP ,
    DFLL_CLOSED_LOOP

};

(yes there's a lil' blank line before the closing brace, that's just how it is, don't come for me 💅)

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🦋 Constants 🦋

• DFLL_UNINITIALIZED — the uninitialized state, i.e. it is not in the hardware bitfield. so like, it exists here but the hardware doesn't even know about it yet 🙈
• DFLL_DISABLED — DFLL is not generating an output clock. clock? never heard of her 💀
• DFLL_OPEN_LOOP — the DVCO is running, but the DFLL is not adjusting voltage. it's just vibing, do not perceive it ⭐
• DFLL_CLOSED_LOOP — DVCO running and the DFLL is adjusting voltage to match the requested rate. main character energy honestly 👑

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💖 Description 💖

So the way this works is: the integer corresponding to the last two states, minus one, is what gets written to the DFLL hardware to change operating modes. no cap, that's the whole trick ✨

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🌈 SEE ALSO 🌈

Kernel file ./drivers/clk/tegra/clk-dfll.c — and here's the whole friend group, in order, exactly like the original line-up:

enum dfll_tune_range(9), struct dfll_rate_req(9), dfll_is_running(9), tegra_dfll_runtime_resume(9), tegra_dfll_runtime_suspend(9), dfll_tune_low(9), dfll_scale_dvco_rate(9), dfll_set_mode(9), dfll_i2c_set_output_enabled(9), dfll_pwm_set_output_enabled(9), dfll_set_force_output_value(9), dfll_set_force_output_enabled(9), dfll_force_output(9), dfll_load_i2c_lut(9), dfll_init_i2c_if(9), dfll_init_out_if(9), find_lut_index_for_rate(9), dfll_calculate_rate_request(9), dfll_set_frequency_request(9), dfll_request_rate(9), dfll_disable(9), dfll_enable(9), dfll_set_open_loop_config(9), dfll_lock(9), dfll_unlock(9), dfll_register_clk(9), dfll_unregister_clk(9), dfll_calc_monitored_rate(9), dfll_read_monitor_rate(9), dfll_set_default_params(9), dfll_init_clks(9), dfll_init(9), tegra_dfll_suspend(9), tegra_dfll_resume(9), dfll_build_i2c_lut(9), read_dt_param(9), dfll_fetch_i2c_params(9), dfll_fetch_common_params(9), tegra_dfll_register(9), tegra_dfll_unregister(9)

like, go read them, iykyk 🫶

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🧚 quick vibe check: the three things to hold onto are the enum name, that "minus one" rule for the last two states, and the fact that DFLL_UNINITIALIZED isn't in the hardware bitfield. everything else is just lore 💜

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okay that's the page!! sourced from ./drivers/clk/tegra, dated October 2026, filed under enum dfll_ctrl_mode(9) — mwah, slay, bye bestie 😭💅