spi_nor_writ...volatile_reg(9)
π spi_nor_writ...volatile_reg(9) β a whole Kernel API Manual moment β¨
okay bestie, buckle up, because we're diving into the Kernel API Manual and this one is genuinely so cute and small, you're gonna eat it up π
πΈ NAME πΈ
spi_nor_write_any_volatile_reg β write any volatile register to flash memory, that's the whole vibe, no cap π
β¨ SYNOPSIS β¨
int spi_nor_write_any_volatile_reg (struct spi_nor *nor , struct
spi_mem_op *op , enum spi_nor_protocol proto );
like, look at her. three args, one int return, main character energy fr fr π
π¦ ARGUMENTS π¦
norβ pointer tostruct spi_nor, the little handle on your whole flash situation π«Άopβ the SPI memory operation. and listen,op->data.bufmust be DMA-able. not "probably fine", not "we'll see" β DMA-able. periodt πprotoβ the SPI protocol you're using for the register operation. pick one, live your truth π
π₯ DESCRIPTION π₯
so the tea is: writing volatile registers is instant according to some manufacturers β and the manpage is out here naming names: Cypress and Micron. so iconic of them π
and because it's instant, there's literally no status polling needed. none. zero. not me refreshing a status register for nothing π
β RETURN β
zero on success, -errno otherwise. that's it, that's the check π
π SEE ALSO π
and now the friend group, because this function does not roll alone β here's the entire squad, plus the kernel file where the magic lives: ./drivers/mtd/spi-nor/core.c π§
spi_nor_get_cmd_ext(9)spi_nor_spimem_setup_op(9)spi_nor_spimem_bounce(9)spi_nor_spimem_exec_op(9)spi_nor_spimem_read_data(9)spi_nor_read_data(9)spi_nor_spimem_write_data(9)spi_nor_write_data(9)spi_nor_read_any_reg(9)spi_nor_write_enable(9)spi_nor_write_disable(9)spi_nor_read_id(9)spi_nor_read_sr(9)spi_nor_read_cr(9)spi_nor_set_4byte_addr_mode_en4b_ex4b(9)spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(9)spi_nor_set_4byte_addr_mode_brwr(9)spi_nor_sr_ready(9)spi_nor_use_parallel_locking(9)spi_nor_ready(9)spi_nor_wait_till_ready_with_timeout(9)spi_nor_wait_till_ready(9)spi_nor_global_block_unlock(9)spi_nor_write_sr(9)spi_nor_write_sr1_and_check(9)spi_nor_write_16bit_sr_and_check(9)spi_nor_write_16bit_cr_and_check(9)spi_nor_write_16bit_sr_cr_and_check(9)spi_nor_write_sr_and_check(9)spi_nor_write_sr_cr_and_check(9)spi_nor_write_sr2(9)spi_nor_read_sr2(9)spi_nor_erase_die(9)spi_nor_div_by_erase_size(9)spi_nor_find_best_erase_type(9)spi_nor_init_erase_cmd(9)spi_nor_destroy_erase_cmd_list(9)spi_nor_init_erase_cmd_list(9)spi_nor_erase_multi_sectors(9)spi_nor_sr1_bit6_quad_enable(9)spi_nor_sr2_bit1_quad_enable(9)spi_nor_sr2_bit7_quad_enable(9)spi_nor_spimem_check_read_pp_op(9)spi_nor_spimem_check_readop(9)spi_nor_spimem_check_pp(9)spi_nor_spimem_adjust_hwcaps(9)spi_nor_set_erase_type(9)spi_nor_mask_erase_type(9)spi_nor_init_uniform_erase_map(9)spi_nor_select_uniform_erase(9)spi_nor_manufacturer_init_params(9)spi_nor_no_sfdp_init_params(9)spi_nor_init_flags(9)spi_nor_init_fixup_flags(9)spi_nor_late_init_params(9)spi_nor_sfdp_init_params_deprecated(9)spi_nor_init_params_deprecated(9)spi_nor_init_default_params(9)spi_nor_init_params(9)spi_nor_quad_enable(9)spi_nor_set_4byte_addr_mode(9)spi_nor_soft_reset(9)
like I said β the whole squad π«Άπ
ok and before I go: that op->data.buf DMA-able thing from up top? not a suggestion bestie, it's giving hard requirement π
so yeah, that's the page! brought to you by ./drivers/mtd/spi-nor in October 2026 β mwah, love u, go write some volatile registers responsibly πβ¨π
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms