spi_nor_sr2_..._quad_enable(9)
β¨ spi_nor_sr2_..._quad_enable(9) β¨
okay so bestie, welcome to the Kernel API Manual entry for spi_nor_sr2_..._quad_enable(9) β yes that title is long, yes it's iconic, no we're not shortening it π
πΈ NAME πΈ
spi_nor_sr2_bit7_quad_enable β sets the QE bit in Status Register 2, and honestly that's the whole personality π
π¦ SYNOPSIS π¦
int spi_nor_sr2_bit7_quad_enable (struct spi_nor *nor );
like, give it a nor and it gives you an int back. simple as that π«Ά
π ARGUMENTS π
norβ pointer to astruct spi_nor. that's it, that's the whole argument list, she travels light β¨
π DESCRIPTION π
So what does she actually do? She sets the Quad Enable (QE) bit in the Status Register 2. periodt π₯
Here's the lore, iykyk: this is one of the procedures to set the QE bit described in the SFDP (JESD216 rev B) specification. But β and this is so real β no manufacturer using this procedure has been identified yet. hence the name of the function π like she exists, she's valid, she's spec-compliant, and literally nobody has shown up to use her yet. main character energy honestly π
β RETURN β
0on success π-errnootherwise π
π SEE ALSO π
Kernel file ./drivers/mtd/spi-nor/core.c and all her besties in the group chat:
spi_nor_get_cmd_ext(9)spi_nor_spimem_setup_op(9)spi_nor_spimem_bounce(9)spi_nor_spimem_exec_op(9)spi_nor_spimem_read_data(9)spi_nor_read_data(9)spi_nor_spimem_write_data(9)spi_nor_write_data(9)spi_nor_read_any_reg(9)spi_nor_write_any_volatile_reg(9)spi_nor_write_enable(9)spi_nor_write_disable(9)spi_nor_read_id(9)spi_nor_read_sr(9)spi_nor_read_cr(9)spi_nor_set_4byte_addr_mode_en4b_ex4b(9)spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(9)spi_nor_set_4byte_addr_mode_brwr(9)spi_nor_sr_ready(9)spi_nor_use_parallel_locking(9)spi_nor_ready(9)spi_nor_wait_till_ready_with_timeout(9)spi_nor_wait_till_ready(9)spi_nor_global_block_unlock(9)spi_nor_write_sr(9)spi_nor_write_sr1_and_check(9)spi_nor_write_16bit_sr_and_check(9)spi_nor_write_16bit_cr_and_check(9)spi_nor_write_16bit_sr_cr_and_check(9)spi_nor_write_sr_and_check(9)spi_nor_write_sr_cr_and_check(9)spi_nor_write_sr2(9)spi_nor_read_sr2(9)spi_nor_erase_die(9)spi_nor_div_by_erase_size(9)spi_nor_find_best_erase_type(9)spi_nor_init_erase_cmd(9)spi_nor_destroy_erase_cmd_list(9)spi_nor_init_erase_cmd_list(9)spi_nor_erase_multi_sectors(9)spi_nor_sr1_bit6_quad_enable(9)spi_nor_sr2_bit1_quad_enable(9)spi_nor_spimem_check_read_pp_op(9)spi_nor_spimem_check_readop(9)spi_nor_spimem_check_pp(9)spi_nor_spimem_adjust_hwcaps(9)spi_nor_set_erase_type(9)spi_nor_mask_erase_type(9)spi_nor_init_uniform_erase_map(9)spi_nor_select_uniform_erase(9)spi_nor_manufacturer_init_params(9)spi_nor_no_sfdp_init_params(9)spi_nor_init_flags(9)spi_nor_init_fixup_flags(9)spi_nor_late_init_params(9)spi_nor_sfdp_init_params_deprecated(9)spi_nor_init_params_deprecated(9)spi_nor_init_default_params(9)spi_nor_init_params(9)spi_nor_quad_enable(9)spi_nor_set_4byte_addr_mode(9)spi_nor_soft_reset(9)
that's the whole page bestie, no gatekeeping π
ngl she's a little niche β one QE bit, one status register, zero known manufacturers β but that's what makes her special π§
π β¨ π π¦ πΈ π π«Ά π π₯ π π β π π π π§ π
shoutout to ./drivers/mtd/spi-nor, dated October 2026, for hosting this whole vibe π mwah, take care of her π
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms