omap3_noncor...e_and_parent(9)

📦 version 7.3.1, in nixpkgs unstable

✨ omap3_noncore_dpll_set_rate_and_parent(9) ✨

okay so bestie 🫶 welcome to the Kernel API Manual — this one is a <cyan>Kernel API</cyan> page about <purple>omap3_noncore_dpll_set_rate_and_parent</purple>, and no I will not be shortening that name, it's giving full government name energy and we respect it 💅

🌸 NAME 🌸

omap3_noncore_dpll_set_rate_and_parent — set rate and parent for a DPLL clock. that's it, that's the whole job, and honestly? iconic.

🎀 SYNOPSIS 🎀

int omap3_noncore_dpll_set_rate_and_parent (struct clk_hw *hw , unsigned
long rate , unsigned long parent_rate , u8 index );

🦋 ARGUMENTS 🦋

  • hw — pointer to the clock you're setting the rate and parent for. the main character we're operating on 👑
  • rate — the target rate for the DPLL. the goal. the dream. 🎯
  • parent_rate — the clock rate of the DPLL's parent. yes it's a whole family tree situation 🌳
  • index — the new parent index for the DPLL: 0 means reference, 1 means bypass. two options, pick your fighter ✨

💖 DESCRIPTION 💖

okay so this function sets the rate and parent for a DPLL clock, both at once, like a multi-tasking queen 💅

here's the tea 🍓: if the new parent is the bypass clock, it only selects the parent — that's it, no rate drama, we're just switching parents and moving on.

otherwise? it proceeds with a rate change, because that will effectively also change the parent as the DPLL is put into locked mode. so like, the rate change is the parent change in disguise. sneaky but slay 🔥

returns 0 with success, and a negative error value otherwise 😭

💀 SEE ALSO 💀

kernel file ./drivers/clk/ti/dpll3xxx.c — and the whole friend group:

ngl bestie, that's a lot of siblings. but every single one of them is in the group chat and we're not leaving anyone on read 💜

🌈 that's the whole page!! sourced straight from ./drivers/clk/ti, dated October 2026, and delivered to you with love, precision, and zero skipped details 🧚‍♀️✨ mwah 💋

📦 where this page comes from