omap3_noncore_dpll_enable(9)

📦 version 7.3.1, in nixpkgs unstable

🎀 omap3_noncore_dpll_enable(9) 🎀

bestie, welcome to the Kernel API Manual entry for omap3_noncore_dpll_enable(9) — it's giving clock-enable main character energy ✨

🌸 NAME 🌸

omap3_noncore_dpll_enable — instruct a DPLL to enter bypass or lock mode, no cap 💅

✨ SYNOPSIS ✨

the whole vibe is literally this:

int omap3_noncore_dpll_enable (struct clk_hw *hw );

🫶 ARGUMENTS 🫶

  • hw — a struct clk_hw containing the pointer to a DPLL struct clk 🦋

💅 DESCRIPTION 💅

okay so this function's whole job is to instruct a non-CORE DPLL to enable — like, to enter bypass or lock mode, periodt. The choice of modes depends on the DPLL's programmed rate: if it is the same as the DPLL's parent clock, it will enter bypass; otherwise, it will enter lock 🔥

This code will wait for the DPLL to indicate readiness before returning, unless the DPLL takes too long to enter the target state. It's intended to be used as the struct clk's enable function 👑

Return vibe check:

  • If DPLL3 was passed in, or the DPLL does not support low-power stop, or if the DPLL took too long to enter bypass or lock, it returns -EINVAL 😭
  • Otherwise, it returns 0 🌈

🧚 SEE ALSO 🧚

go read these too, bestie 💜

Kernel file: ./drivers/clk/ti/dpll3xxx.c

cute sign-off time 🎀 this page's source/version spot is ./drivers/clk/ti, it's dated October 2026, and you've been reading the omap3_noncore_dpll_enable(9) manual page. bye bestie, go clock responsibly 🌸💋

📦 where this page comes from