omap3_dpll4_set_rate(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… omap3_dpll4_set_rate(9) πŸ’…

okay bestie, welcome to the Kernel API Manual ✨ β€” yes, that Kernel API Manual, the one with the clock driver lore. today's main character is omap3_dpll4_set_rate, and she is literally the one who sets the rate for omap3 per-dpll. no cap.


🌸 NAME 🌸

omap3_dpll4_set_rate β€” set rate for omap3 per-dpll. that's it, that's the vibe check, and she passed 🫢


πŸŽ€ SYNOPSIS πŸŽ€

int omap3_dpll4_set_rate (struct clk_hw *hw , unsigned long rate ,
       unsigned long parent_rate );

three args, one int, zero chill. let's get into it πŸ’–


✨ ARGUMENTS ✨

  • hw β€” the clock you wanna change. like, the actual clock. this is her πŸ”₯
  • rate β€” the target rate for the clock. the goal. the dream. the number we're manifesting πŸ’«
  • parent_rate β€” the clock rate of the DPLL parent, aka where she came from, aka her roots 🌱

πŸ¦‹ DESCRIPTION πŸ¦‹

so here's the tea 🍡: this function checks whether the current SoC actually supports the per-dpll reprogram operation or not β€” vibe check on the silicon first, always β€” and then does the rate change if it's supported.

returns -EINVAL if it's not supported (rip, not supported, we don't know her πŸ’€), 0 for success (slay, we love a win πŸ‘‘), and any potential error codes from the clock rate change (yeah, those can happen too, it's giving realistic πŸ™ˆ).


🌈 SEE ALSO 🌈

literally the whole friend group, the entire clock squad, all of them, iykyk:

Kernel file ./drivers/clk/ti/dpll3xxx.c _omap3_noncore_dpll_lock(9), _omap3_noncore_dpll_bypass(9), _omap3_noncore_dpll_stop(9), _lookup_dco(9), _lookup_sddiv(9), omap3_noncore_dpll_ssc_program(9), omap3_noncore_dpll_program(9), omap3_dpll_recalc(9), omap3_noncore_dpll_enable(9), omap3_noncore_dpll_disable(9), omap3_noncore_dpll_determine_rate(9), omap3_noncore_dpll_set_parent(9), omap3_noncore_dpll_set_rate(9), omap3_noncore_dpll_set_rate_and_parent(9), omap3_dpll_autoidle_read(9), omap3_dpll_allow_idle(9), omap3_dpll_deny_idle(9), omap3_clkoutx2_recalc(9), omap3_core_dpll_save_context(9), omap3_core_dpll_restore_context(9), omap3_noncore_dpll_save_context(9), omap3_noncore_dpll_restore_context(9), omap3_dpll4_set_rate_and_parent(9), omap3_dpll5_set_rate(9)

yes i listed every single one, bestie. every. single. one. we do not skip the boring parts in this house πŸ’…

and that's the whole page, mwah 😘 sourced straight from ./drivers/clk/ti, dated October 2026, brought to you by the Kernel API Manual, which is honestly iconic for this. periodt. πŸ§šβ€β™€οΈπŸ’œ

πŸ“¦ where this page comes from