omap3_noncore_dpll_set_rate(9)

📦 version 7.3.1, in nixpkgs unstable

💅 omap3_noncore_dpll_set_rate(9) — like, the Kernel API Manual page you actually wanna read 🎀

okay so bestie, welcome to the Kernel API Manual entry for omap3_noncore_dpll_set_rate(9) — yes that's a whole mouthful, yes it's iconic, and yes we're gonna get through it together ✨

🌸 NAME 🌸

omap3_noncore_dpll_set_rate — set rate for a DPLL clock 💫

🦋 SYNOPSIS 🦋

int omap3_noncore_dpll_set_rate (struct clk_hw *hw , unsigned long rate
, unsigned long parent_rate );

literally the whole signature, character for character, no cap 🔥

💖 ARGUMENTS 💖

  • hw — pointer to the clock to set parent for 🫶
  • rate — target rate for the clock, like the glow-up goal 🌟
  • parent_rate — rate of the parent clock, the vibe it's inheriting from 👑

✨ DESCRIPTION ✨

So here's the tea 🍓 — this function sets rate for a DPLL clock.

First thing it does? It checks if the clock parent is the reference clock. And bestie, if it is — that's bypass mode — and in bypass mode the rate of the clock can't be changed, periodt. 💀 No negotiating, no workarounds, it's just not happening.

If the vibe check passes, it proceeds with the rate change operation 💅

Returns 0 on success, and a negative error value otherwise 😭 (so like, always check your return value, iykyk).

👑 SEE ALSO 👑

Kernel file ./drivers/clk/ti/dpll3xxx.c — and the whole friend group 🫶:

💀 friendly reminder: in bypass mode the rate can't be changed. That's not a suggestion, that's the whole bit.

and that's the page!! 🧚‍♀️ this lil masterpiece lives in ./drivers/clk/ti and it's dated October 2026, source and all — mwah, slay, go set some clock rates responsibly bestie 💜🎀💅

📦 where this page comes from