omap3_nonco...l_set_parent(9)

📦 version 7.3.1, in nixpkgs unstable

💅 omap3_noncore_dpll_set_parent(9) ✨

okay so bestie, welcome to the Kernel API Manual 🫶 this one's a function page, it lives in the kernel API docs, and it's literally about telling a DPLL clock who its parent is. no cap.

🎀 NAME 🎀

omap3_noncore_dpll_set_parent — the function that sets the parent for a DPLL clock 💫

✨ SYNOPSIS ✨

int omap3_noncore_dpll_set_parent (struct clk_hw *hw , u8 index );

that's the whole signature, character for character, no edits from me 🌸

🦋 ARGUMENTS 🦋

  • hw — a pointer to the clock you're setting the parent for 🕰️ like, this is the clock in question, the main character.
  • index — the parent index you want to select 🔢 which parent are we picking? this number decides.

💖 DESCRIPTION 💖

so what it does: it sets the parent for a DPLL clock 👑 and the way it does that is by putting the DPLL into bypass or locked mode — one of the two, depending on what's going on 🔥

and it returns 0 on success, or a negative error value otherwise 😭 so like, check your return value, fr fr, don't just assume it slayed.

🌈 SEE ALSO 🌈

the whole friend group, all from the kernel file ./drivers/clk/ti/dpll3xxx.c 📁:

like, that's the entire group chat, go say hi 💜

🧚 sign-off 🧚

this little page comes from ./drivers/clk/ti, it's dated October 2026, and the manual tag on it is omap3_nonco...l_set_parent(9) 🎀 that's it, that's the whole vibe. bye bestie, go set some parents 🦋💅

📦 where this page comes from