_omap3_noncore_dpll_bypass(9)

📦 version 7.3.1, in nixpkgs unstable

💅 _omap3_noncore_dpll_bypass(9) ✨

okay so this is a page from the Kernel API Manual, and bestie, it's giving "tiny function, big responsibilities." let's get into it 🫶

🌸 NAME 🌸

_omap3_noncore_dpll_bypass — literally just tells a DPLL to go bypass mode and then waits for it to be ready 💖

🦋 SYNOPSIS 🦋

int _omap3_noncore_dpll_bypass (struct clk_hw_omap *clk );

🎀 ARGUMENTS 🎀

  • clk — a pointer to a DPLL struct clk, that's it, that's the whole arg list ✨

👑 DESCRIPTION 👑

so what this does is it instructs a non-CORE DPLL to enter low-power bypass mode. 🧚 in bypass mode, the DPLL's rate gets set equal to its parent clock's rate — like, it just copies the parent's vibe, no cap.

then it waits for the DPLL to report readiness before returning, because we don't leave the group chat until everyone's actually there 💅

it also saves and restores the DPLL's autoidle state across the enable, per the CDP code. iconic behavior honestly.

return values, listen up:

  • if the DPLL entered bypass mode successfully → returns 0 ✅
  • if the DPLL did not enter bypass in the time allotted → returns -EINVAL 😭
  • if DPLL3 was passed in → returns -EINVAL 🙈
  • if the DPLL just does not support low-power bypass → returns -EINVAL 💀
so yeah, -EINVAL is doing a lot of heavy lifting here. three separate ways to get it. know them, love them, fear them.

🌈 SEE ALSO 🌈

the kernel file ./drivers/clk/ti/dpll3xxx.c is where this lives, and here's the whole friend group 👯‍♀️✨:

that's the whole page babes, go read the source at ./drivers/clk/ti — this edition dropped October 2026, so it's fresh 🍓 mwah, slay, bye 💜🎀

📦 where this page comes from