omap3_dpll4...e_and_parent(9)

🦋 omap3_dpll4...e_and_parent(9) 🦋

okay bestie, this is the Kernel API Manual page for the function with the iconic long name 💅

💖 NAME 💖

omap3_dpll4_set_rate_and_parent — set rate and parent for omap3 per-dpll

✨ SYNOPSIS ✨

int omap3_dpll4_set_rate_and_parent (struct clk_hw *hw , unsigned long
       rate , unsigned long parent_rate , u8 index );

🎀 ARGUMENTS 🎀

• hw — clock to change
• rate — target rate for clock
• parent_rate — rate of the parent clock
• index — parent index, 0 - reference clock, 1 - bypass clock

💅 DESCRIPTION 💅

okay so first it checks whether the current SoC supports the per-dpll reprogram operation or not. If it does, then it does the rate + parent change. It returns -EINVAL if that's not supported, 0 for success, and there can be potential error codes coming from the clock rate change. periodt ✨

🌈 SEE ALSO 🌈

Kernel file ./drivers/clk/ti/dpll3xxx.c is right there in the mix, and the whole squad is:

• _omap3_noncore_dpll_lock(9)
• _omap3_noncore_dpll_bypass(9)
• _omap3_noncore_dpll_stop(9)
• _lookup_dco(9)
• _lookup_sddiv(9)
• omap3_noncore_dpll_ssc_program(9)
• omap3_noncore_dpll_program(9)
• omap3_dpll_recalc(9)
• omap3_noncore_dpll_enable(9)
• omap3_noncore_dpll_disable(9)
• omap3_noncore_dpll_determine_rate(9)
• omap3_noncore_dpll_set_parent(9)
• omap3_noncore_dpll_set_rate(9)
• omap3_noncore_dpll_set_rate_and_parent(9)
• omap3_dpll_autoidle_read(9)
• omap3_dpll_allow_idle(9)
• omap3_dpll_deny_idle(9)
• omap3_clkoutx2_recalc(9)
• omap3_core_dpll_save_context(9)
• omap3_core_dpll_restore_context(9)
• omap3_noncore_dpll_save_context(9)
• omap3_noncore_dpll_restore_context(9)
• omap3_dpll4_set_rate(9)
• omap3_dpll5_set_rate(9)

okay that's the whole page bestie, no cap 💖 This one comes from source/version ./drivers/clk/ti, dated October 2026, and it's literally the omap3_dpll4...e_and_parent(9) page. 🎀