section 9 · Kernel routines 🧠

C (continued)

• clean_cache_range(9)write back a cache range with CLWB✨
• clean_fn(9)Cleanup function to remove invalid keys from the cache tree.✨
• clean_journal(9)mark a dirty journal as being clean✨
• clean_record_pte(9)Clean a pte and record its address space offset in a bitmap✨
• clean_record_shared_mapping_range(9)Clean and record all ptes in an address space range✨
• clean_registry(9)- clean up registry memory in case of error✨
• cleanup_aer_uncorrect_error_status(9)Cleanup PCI AER uncorrectable error status✨
• cleanup_cgroup_environment(9)Cleanup Cgroup Testing Environment✨
• cleanup_classid_environment(9)Cleanup the cgroupv1 net_cls environment✨
• cleanup_cpu_mmu_context(9)Clean up MMU details for this CPU (newly offlined)✨
• cleanup_offline_cgwb(9)detach associated inodes✨
• cleanup_sdt_note_list(9)free the sdt notes' list✨
• cleanup_socket_xprt(9)remove xprtsock's sysctls, unregister✨
• cleanup_srcu_struct(9)deconstruct a sleep-RCU structure✨
• cleanup_sync_octeon_time_wq(9)destroy wq✨
• clear_all_interrupts(9)Clear all interrupts of I2C Controller✨
• clear_and_wake_up_bit(9)clear a bit and wake up anyone waiting on that bit✨
• clear_bit(9)Clears a bit in memory✨
• clear_bit_unlock(9)Clear a bit in memory, for unlock✨
• clear_event_triggers(9)Clear all triggers associated with a trace array✨
• clear_exclusive_cxl_commands(9)atomically enable user cxl commands✨
• clear_flush_young_ptes(9)Mark PTEs that map consecutive pages of the same folio as old and flush the TLB.✨
• clear_full_ptes(9)Clear present PTEs that map consecutive pages of the same folio.✨
• clear_io_resources(9)set the IO resources as not active in the NIC✨
• clear_local_APIC(9)shutdown the local APIC✨
• clear_mapped_location(9)Clear a data_vio's mapped block location, setting it to be unmapped.✨
• clear_nlink(9)directly zero an inode's link count✨
• clear_nonpresent_ptes(9)Clear multiple non-present PTEs which are consecutive in the pgtable.✨
• clear_page(9)clear a page using a kernel virtual address.✨
• clear_pages(9)clear a page range for kernel-internal use.✨
• clear_pending(9)clear the pending bit.✨
• clear_pending_set_locked(9)take ownership and clear the pending bit.✨
• clear_pfnblock_bit(9)Clear a standalone bit of a pageblock✨
• clear_ptes(9)Clear present PTEs that map consecutive pages of the same folio.✨
• clear_root_gid(9)Set GuestCtl1.RID for normal root operation.✨
• clear_selection(9)remove current selection✨
• clear_sge_ctxt(9)completely clear an SGE context✨
• clear_tasks_mm_cpumask(9)Safely clear tasks' mm_cpumask for a CPU✨
• clear_unrhdr(9)kernel unit number allocator✨
• clear_unrhdr(9freebsd)kernel unit number allocator✨
• clear_update_marker(9)clear update marker.✨
• clear_user(9)Zero a block of memory in user space.✨
• clear_user_highpage(9)clear a page to be mapped to user space✨
• clear_user_highpages(9)clear a page range to be mapped to user space✨
• clear_user_page(9)clear a page to be mapped to user space✨
• clear_user_pages(9)clear a page range to be mapped to user space✨
• clear_va_list_locked(9)free virtual addresses list.✨
• clear_young_dirty_ptes(9)Mark PTEs that map consecutive pages of the same folio as old/clean.✨
• clflush_cache_range(9)flush a cache range with clflush✨
• clk framework flags(9)✨
• clk notifier callback types(9)✨
• clk_bulk_disable(9)inform the system when the set of clks is no longer required.✨
• clk_bulk_enable(9)inform the system when the set of clks should be running.✨
• clk_bulk_get(9)lookup and obtain a number of references to clock producer.✨
• clk_bulk_get_all(9)lookup and obtain all available references to clock producer.✨
• clk_bulk_get_optional(9)lookup and obtain a number of references to clock producer✨
• clk_bulk_prepare(9)prepare a set of clocks✨
• clk_bulk_put(9)"free" the clock source✨
• clk_bulk_put_all(9)"free" all the clock source✨
• clk_bulk_unprepare(9)undo preparation of a set of clock sources✨
• clk_core_get(9)Find the clk_core parent of a clk✨
• clk_core_link_consumer(9)Add a clk consumer to the list of consumers in a clk_core✨
• clk_core_unlink_consumer(9)Remove a clk consumer from the list of consumers in a clk_core✨
• clk_debug_init(9)lazily populate the debugfs clk directory✨
• clk_debug_register(9)add a clk node to the debugfs clk directory✨
• clk_determine_rate_noop(9)clk_ops::determine_rate noop implementation✨
• clk_disable(9)inform the system when the clock source is no longer required.✨
• clk_disable_regmap(9)standard disable() for regmap users✨
• clk_divider_restore_context(9)restore the saved the divider value✨
• clk_divider_save_context(9)Save the divider value✨
• clk_drop_range(9)Reset any range set on that clock✨
• clk_enable(9)inform the system when the clock source should be running.✨
• clk_enable_regmap(9)standard enable() for regmap users✨
• clk_gate_restore_context(9)restore context for poweroff✨
• clk_generated_startup(9)Initialize a given clock to its default parent and divisor parameter.✨
• clk_get(9)lookup and obtain a reference to a clock producer.✨
• clk_get_accuracy(9)obtain the clock accuracy in ppb (parts per billion) for a clock source.✨
• clk_get_kunit(9)Test managed clk_get()✨
• clk_get_optional(9)lookup and obtain a reference to an optional clock producer.✨
• clk_get_parent(9)get the parent clock source for this clock✨
• clk_get_phase(9)return the phase shift of a clock signal✨
• clk_get_rate(9)obtain the current clock rate (in Hz) for a clock source. This is only valid once the clock source has been enabled.✨
• clk_get_scaled_duty_cycle(9)return the duty cycle ratio of a clock signal✨
• clk_get_sys(9)get a clock based upon the device name✨
• clk_has_parent(9)check if a clock is a possible parent for another✨
• clk_hw_create_clk(9)Allocate and link a clk consumer to a clk_core given a clk_hw✨
• clk_hw_forward_rate_request(9)Forwards a clk_rate_request to a clock's parent✨
• clk_hw_get_clk(9)get clk consumer given an clk_hw✨
• clk_hw_get_clk_kunit(9)Test managed clk_hw_get_clk()✨
• clk_hw_get_clk_prepared_enabled_kunit(9)Test managed clk_hw_get_clk() + clk_prepare_enable()✨
• clk_hw_get_dev(9)get device from an hardware clock.✨
• clk_hw_get_of_node(9)get device_node from a hardware clock.✨
• clk_hw_get_parent_index(9)return the index of the parent clock✨
• clk_hw_init_rate_request(9)Initializes a clk_rate_request✨
• clk_hw_register(9)register a clk_hw and return an error code✨
• clk_hw_register_clkdev(9)register one clock lookup for a struct clk_hw✨
• clk_hw_register_divider(9)register a divider clock with the clock framework✨
• clk_hw_register_divider_parent_data(9)register a divider clock with the clock framework✨
• clk_hw_register_divider_parent_hw(9)register a divider clock with the clock framework✨
• clk_hw_register_divider_table(9)register a table based divider clock with the clock framework✨
• clk_hw_register_divider_table_parent_data(9)register a table based divider clock with the clock framework✨
• clk_hw_register_divider_table_parent_hw(9)register a table based divider clock with the clock framework✨
• clk_hw_register_fixed_rate(9)register fixed-rate clock with the clock framework✨
• clk_hw_register_fixed_rate_kunit(9)Test managed __clk_hw_register_fixed_rate()✨
• clk_hw_register_fixed_rate_parent_accuracy(9)register fixed-rate clock with the clock framework✨
• clk_hw_register_fixed_rate_parent_data(9)register fixed-rate clock with the clock framework✨
• clk_hw_register_fixed_rate_parent_hw(9)register fixed-rate clock with the clock framework✨
• clk_hw_register_fixed_rate_with_accuracy(9)register fixed-rate clock with the clock framework✨
• clk_hw_register_fixed_rate_with_accuracy_parent_data(9)register fixed- rate clock with the clock framework✨
• clk_hw_register_fixed_rate_with_accuracy_parent_hw(9)register fixed-rate clock with the clock framework✨
• clk_hw_register_gate(9)register a gate clock with the clock framework✨
• clk_hw_register_gate_parent_data(9)register a gate clock with the clock framework✨
• clk_hw_register_gate_parent_hw(9)register a gate clock with the clock framework✨
• clk_hw_register_kunit(9)Test managed clk_hw_register()✨
• clk_hw_round_rate(9)round the given rate for a hw clk✨
• clk_hw_unregister(9)unregister a currently registered clk_hw✨
• clk_hw_unregister_divider(9)unregister a clk divider✨
• clk_hw_unregister_fixed_rate_kunit(9)Test managed clk_hw_unregister_fixed_rate()✨
• clk_imx_acm_attach_pm_domains(9)attach multi power domains✨
• clk_imx_acm_detach_pm_domains(9)detach multi power domains✨
• clk_is_enabled_regmap(9)standard is_enabled() for regmap users✨
• clk_is_enabled_when_prepared(9)indicate if preparing a clock also enables it.✨
• clk_is_match(9)check if two clk's point to the same hardware clock✨
• clk_lucid_5lpe_pll_configure(9)configure the lucid 5lpe pll✨
• clk_mux_restore_context(9)Restore the parent in the mux✨
• clk_mux_save_context(9)Save the parent selected in the mux✨
• clk_notifier_register(9)register a clock rate-change notifier callback✨
• clk_notifier_unregister(9)unregister a clock rate-change notifier callback✨
• clk_pm_runtime_get_all(9)Runtime "get" all clk provider devices✨
• clk_pm_runtime_put_all(9)Runtime "put" all clk provider devices✨
• clk_prepare(9)prepare a clock source✨
• clk_prepare_enable_kunit(9)Test managed clk_prepare_enable()✨
• clk_put(9)"free" the clock source✨
• clk_rate_exclusive_get(9)get exclusivity over the rate control of a producer✨
• clk_rate_exclusive_put(9)release exclusivity over the rate control of a producer✨
• clk_rcg2_split_div(9)Split multiplier that doesn't fit in n neither in pre_div.✨
• clk_register(9)allocate a new clock, register it and return an opaque cookie✨
• clk_register_clkdev(9)register one clock lookup for a struct clk✨
• clk_register_divider(9)register a divider clock with the clock framework✨
• clk_register_divider_table(9)register a table based divider clock with the clock framework✨
• clk_register_psc(9)register psc clock✨
• clk_register_zynq_pll(9)Register PLL with the clock framework✨
• clk_restore_context(9)restore clock context after poweroff✨
• clk_round_rate(9)adjust a rate to the exact rate a clock can provide✨
• clk_save_context(9)save clock context for poweroff✨
• clk_set_duty_cycle(9)adjust the duty cycle ratio of a clock signal✨
• clk_set_max_rate(9)set a maximum clock rate for a clock source✨
• clk_set_min_rate(9)set a minimum clock rate for a clock source✨
• clk_set_parent(9)set the parent clock source for this clock✨
• clk_set_phase(9)adjust the phase shift of a clock signal✨
• clk_set_rate(9)set the clock rate for a clock source✨
• clk_set_rate_exclusive(9)set the clock rate and claim exclusivity over clock source✨
• clk_set_rate_range(9)set a rate range for a clock source✨
• clk_trion_pll_configure(9)configure the trion pll✨
• clk_unprepare(9)undo preparation of a clock source✨
• clk_unregister(9)unregister a currently registered clock✨
• clkdev_create(9)allocate and add a clkdev lookup structure✨
• clkdev_hw_create(9)allocate and add a clkdev lookup structure✨
• clkdm_add_autodeps(9)add auto sleepdeps/wkdeps to clkdm upon clock enable✨
• clkdm_add_sleepdep(9)add a sleep dependency from clkdm2 to clkdm1✨
• clkdm_add_wkdep(9)add a wakeup dependency from clkdm2 to clkdm1✨
• clkdm_allow_idle(9)enable hwsup idle transitions for clkdm✨
• clkdm_allow_idle_nolock(9)enable hwsup idle transitions for clkdm✨
• clkdm_clear_all_sleepdeps(9)remove all sleep dependencies from target clkdm✨
• clkdm_clear_all_wkdeps(9)remove all wakeup dependencies from target clkdm✨
• clkdm_clk_disable(9)remove an enabled downstream clock from this clkdm✨
• clkdm_clk_enable(9)add an enabled downstream clock to this clkdm✨
• clkdm_complete_init(9)set up the clockdomain layer✨
• clkdm_del_autodeps(9)remove auto sleepdeps/wkdeps from clkdm✨
• clkdm_del_sleepdep(9)remove a sleep dependency from clkdm2 to clkdm1✨
• clkdm_del_wkdep(9)remove a wakeup dependency from clkdm2 to clkdm1✨
• clkdm_deny_idle(9)disable hwsup idle transitions for clkdm✨
• clkdm_deny_idle_nolock(9)disable hwsup idle transitions for clkdm✨
• clkdm_for_each(9)call function on each registered clockdomain✨
• clkdm_get_pwrdm(9)return a ptr to the pwrdm that this clkdm resides in✨
• clkdm_hwmod_disable(9)remove an enabled downstream hwmod from this clkdm✨
• clkdm_hwmod_enable(9)add an enabled downstream hwmod to this clkdm✨
• clkdm_lookup(9)look up a clockdomain by name, return a pointer✨
• clkdm_read_sleepdep(9)read sleep dependency state from clkdm2 to clkdm1✨
• clkdm_read_wkdep(9)read wakeup dependency state from clkdm2 to clkdm1✨
• clkdm_register_autodeps(9)register autodeps (if required)✨
• clkdm_register_clkdms(9)register SoC clockdomains✨
• clkdm_register_platform_funcs(9)register clockdomain implementation fns✨
• clkdm_restore_context(9)Restores the context for each registered clkdm✨
• clkdm_save_context(9)Saves the context for each registered clkdm✨
• clkdm_sleep(9)force clockdomain sleep transition✨
• clkdm_sleep_nolock(9)force clockdomain sleep transition (lockless)✨
• clkdm_wakeup(9)force clockdomain wakeup transition✨
• clkdm_wakeup_nolock(9)force clockdomain wakeup transition (lockless)✨
• clo_func(9)Emulate a CLO instruction✨
• clock(9)handy time utilities✨
• Clock Generated by PLL, rate set and enabled by bootloader(9)✨
• clock2alarm(9)helper that converts from clockid to alarmtypes✨
• clock_t_to_jiffies(9)Convert clock_t to jiffies✨
• clockevent_delta2ns(9)Convert a latch value (device ticks) to nanoseconds✨
• clockevents_config_and_register(9)Configure and register a clock event device✨
• clockevents_exchange_device(9)release and request clock devices✨
• clockevents_increase_min_delta(9)raise minimum delta of a clock event device✨
• clockevents_program_event(9)Reprogram the clock event device.✨
• clockevents_program_min_delta(9)Set clock event device to the minimum delay.✨