clk_hw_regis...te_parent_hw(9)
π NAME π
clk_hw_register_gate_parent_hw β bestie, it registers a gate clock with the clock framework π (yes, this is a Kernel API Manual page, and yes it's about to be your new obsession β¨)
β¨ SYNOPSIS β¨
clk_hw_register_gate_parent_hw (dev , name , parent_hw , flags , reg ,
bit_idx , clk_gate_flags , lock );
πΈ ARGUMENTS πΈ
okay so here's the whole cast, no cap π
devβ the device that is registering this clock. it's giving "who's the parent here" energy π«Άnameβ the name of this clock. name your child, legend β¨parent_hwβ pointer to parent clk. the main character's main character π πflagsβ framework-specific flags for this clock. iykyk πregβ register address to control gating of this clock. this is the address, fr fr πbit_idxβ which bit in the register controls gating of this clock. one single bit carries the entire vibe check πclk_gate_flagsβ gate-specific flags for this clock. different flags, different vibe π«lockβ shared register lock for this clock. everybody shares, we love to see it π
π¦ SEE ALSO π¦
the whole friend group, literally π β
- Kernel file
./include/linux/clk-provider.h clk framework flags(9)struct clk_rate_request(9)struct clk_duty(9)struct clk_spread_spectrum(9)struct clk_ops(9)struct clk_parent_data(9)struct clk_init_data(9)struct clk_hw(9)struct clk_fixed_rate(9)clk_hw_register_fixed_rate(9)devm_clk_hw_register_fixed_rate(9)devm_clk_hw_register_fixed_rate_parent_data(9)clk_hw_register_fixed_rate_parent_hw(9)clk_hw_register_fixed_rate_parent_data(9)clk_hw_register_fixed_rate_with_accuracy(9)clk_hw_register_fixed_rate_with_accuracy_parent_hw(9)clk_hw_register_fixed_rate_with_accuracy_parent_data(9)clk_hw_register_fixed_rate_parent_accuracy(9)struct clk_gate(9)clk_hw_register_gate(9)clk_hw_register_gate_parent_data(9)devm_clk_hw_register_gate(9)devm_clk_hw_register_gate_parent_hw(9)devm_clk_hw_register_gate_parent_data(9)struct clk_divider(9)clk_register_divider(9)clk_hw_register_divider(9)clk_hw_register_divider_parent_hw(9)clk_hw_register_divider_parent_data(9)clk_hw_register_divider_table(9)clk_hw_register_divider_table_parent_hw(9)clk_hw_register_divider_table_parent_data(9)devm_clk_hw_register_divider(9)devm_clk_hw_register_divider_parent_hw(9)devm_clk_hw_register_divider_parent_data(9)devm_clk_hw_register_divider_table(9)struct clk_mux(9)struct clk_fixed_factor(9)devm_clk_hw_register_fixed_factor_parent_hw(9)struct clk_fractional_divider(9)struct clk_multiplier(9)clk_hw_get_dev(9)clk_hw_get_of_node(9)
that's the whole page, bestie β every flag, every argument, every single SEE ALSO, all intact π go forth and register that gate clock π§ββοΈ
and that's a wrap π¬ this iconic little page lives in ./include/linux and it's dated October 2026 β see you in the next kernel release, mwah π slay
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms