ice_write_64...p_reg_eth56g(9)

📦 version 7.3.1, in nixpkgs unstable

💅 ice_write_64b_ptp_reg_eth56g — a Kernel API Manual moment

okay so bestie, welcome to the Kernel API Manual page for ice_write_64b_ptp_reg_eth56g(9) — yes the header up top is truncated to ice_write_64...p_reg_eth56g(9) because someone let the filename cook too hard, but we know her full name and we respect her 💖

✨ NAME ✨

ice_write_64b_ptp_reg_eth56g — write a 64bit value to PHY registers 🎀

🦋 SYNOPSIS 🦋

int ice_write_64b_ptp_reg_eth56g (struct ice_hw *hw , u8 port , u16
low_addr , u64 val );

🌸 ARGUMENTS 🌸

  • hw — pointer to the HW struct, the main character honestly 👑
  • port — the PHY port to read from
  • low_addr — offset of the lower register to read from
  • val — the contents of the 64bit value to write to PHY

💜 DESCRIPTION 💜

So what she does is: check if the caller has specified a known 64 bit register offset — vibe check on the offset, basically — and then write the 64bit value to the two associated 32bit PHY registers. Two registers. One 64bit value. She's splitting it. It's giving teamwork fr fr 🫶

🔥 RETURN 🔥

  • 0 — success, we ate 💅
  • EINVAL — not a 64 bit register (so like… the offset did NOT pass the vibe check 🙈)
  • other — failed to write to PHY, and honestly? tragic 😭

⭐ SEE ALSO ⭐

Kernel file ./drivers/net/ethernet/intel/ice/ice_ptp_hw.c

and now, bestie, the friend group. every single one of them. no cap, no skips 💀

like I said. the whole group chat 🫶

tiny heads up bestie: the EINVAL case is literally just "that offset isn't a known 64 bit register" — she's not being mean, she's being precise 💅

🌈 and that's the page!! brought to you from ./drivers/net/ethernet/intel/ice, October 2026 edition — ice_write_64...p_reg_eth56g(9), still iconic, still truncated in the header, still slaying ✨🎀💖

📦 where this page comes from