ice_phy_cfg_parpcs_e82x(9)

📦 version 7.3.1, in nixpkgs unstable

✨ hey bestie, you opened the Kernel API Manual page for ice_phy_cfg_parpcs_e82x ✨

✨ NAME ✨

ice_phy_cfg_parpcs_e82x — configure TUs per PAR/PCS clock cycle 💅

🛠 SYNOPSIS 🛠

int ice_phy_cfg_parpcs_e82x (struct ice_hw *hw , u8 port );

🎀 ARGUMENTS 🎀

  • hw — pointer to the HW struct 🫶
  • port — the port to configure 💖

💖 DESCRIPTION 💖

okay so this one configures the number of TUs for the PAR and PCS clocks used as part of the timestamp calibration process. It depends on the link speed, because the PHY uses different markers depending on the speed. no cap. 🦋

Here’s the marker menu, bestie:

  • 1Gb/10Gb/25Gb
    • Tx/Rx PAR/PCS markers
  • 25Gb RS
    • Tx/Rx Reed Solomon gearbox PAR/PCS markers
  • 40Gb/50Gb
    • Tx/Rx PAR/PCS markers
    • Rx Deskew PAR/PCS markers
  • 50G RS and 100GB RS
    • Tx/Rx Reed Solomon gearbox PAR/PCS markers
    • Rx Deskew PAR/PCS markers
    • Tx PAR/PCS markers

To calculate the conversion, we use the PHC clock frequency (cycles per second), the increment value (TUs per cycle), and the related PHY clock frequency to calculate the TUs per unit of the PHY link clock. The following table shows how the units convert:

cycles |  TUs  | second
-------+-------+--------
second | cycle | cycles

For each conversion register, look up the appropriate frequency from the e822 PAR/PCS table and calculate the TUs per unit of that clock. Program this to the appropriate register, preparing hardware to perform timestamp calibration to calculate the total Tx or Rx offset to adjust the timestamp in order to calibrate for the internal PHY delays. literally the whole point, periodt. 🔥

heads up, bestie: the increment value ranges up to ~34 bits, and the clock frequency is ~29 bits, so multiplying them together should fit within the 64 bit arithmetic. math is mathing. 🧚

🦋 SEE ALSO 🦋

made with 💖 from ./drivers/net/ethernet/intel/ice · date/version vibe: October 2026 · page: ice_phy_cfg_parpcs_e82x(9) 🌈

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