ice_phy_cfg_lane_e82x(9)
π NAME π
okay so bestie, this page is ice_phy_cfg_lane_e82x(9) from the Kernel API Manual, and it's giving: Configure PHY quad for single/multi-lane timestamp. That's the whole assignment, no cap. π
β¨ SYNOPSIS β¨
void ice_phy_cfg_lane_e82x (struct ice_hw *hw , u8 port );
π«Ά ARGUMENTS π«Ά
hwβ pointer to HW struct. literally the hardware struct, bestie.portβ to configure the quad for. that's the port in question π
π SEE ALSO π
Kernel file: ./drivers/net/ethernet/intel/ice/ice_ptp_hw.c β that's where this lives, periodt.
the full cross-reference squad, every (9) intact, no skips:
ice_get_ptp_src_clock_index(9)ice_ptp_read_src_incval(9)ice_ptp_tmr_cmd_to_src_reg(9)ice_ptp_tmr_cmd_to_port_reg(9)ice_ptp_src_cmd(9)ice_ptp_exec_tmr_cmd(9)ice_ptp_cfg_sync_delay(9)ice_ptp_init_phc_e825c(9)ice_ptp_get_dest_dev_e825(9)ice_write_phy_eth56g(9)ice_read_phy_eth56g(9)ice_get_serdes_ref_sel_e825c(9)ice_phy_res_address_eth56g(9)ice_write_port_eth56g(9)ice_read_port_eth56g(9)ice_write_ptp_reg_eth56g(9)ice_write_mac_reg_eth56g(9)ice_write_xpcs_reg_eth56g(9)ice_read_ptp_reg_eth56g(9)ice_read_mac_reg_eth56g(9)ice_read_gpcs_reg_eth56g(9)ice_read_port_mem_eth56g(9)ice_write_port_mem_eth56g(9)ice_write_quad_ptp_reg_eth56g(9)ice_read_quad_ptp_reg_eth56g(9)ice_is_64b_phy_reg_eth56g(9)ice_is_40b_phy_reg_eth56g(9)ice_read_64b_phy_reg_eth56g(9)ice_read_64b_ptp_reg_eth56g(9)ice_write_40b_phy_reg_eth56g(9)ice_write_40b_ptp_reg_eth56g(9)ice_write_64b_phy_reg_eth56g(9)ice_write_64b_ptp_reg_eth56g(9)ice_read_ptp_tstamp_eth56g(9)ice_clear_ptp_tstamp_eth56g(9)ice_ptp_reset_ts_memory_eth56g(9)ice_ptp_prep_port_time_eth56g(9)ice_ptp_prep_phy_time_eth56g(9)ice_ptp_prep_port_adj_eth56g(9)ice_ptp_prep_phy_adj_eth56g(9)ice_ptp_prep_phy_incval_eth56g(9)ice_ptp_read_port_capture_eth56g(9)ice_ptp_write_port_cmd_eth56g(9)ice_phy_get_speed_eth56g(9)ice_phy_cfg_parpcs_eth56g(9)ice_phy_cfg_ptp_1step_eth56g(9)mul_u32_u32_fx_q9(9)add_u32_u32_fx(9)ice_ptp_calc_bitslip_eth56g(9)ice_ptp_calc_deskew_eth56g(9)ice_phy_set_offsets_eth56g(9)ice_phy_cfg_mac_eth56g(9)ice_phy_cfg_intr_eth56g(9)ice_read_phy_and_phc_time_eth56g(9)ice_sync_phy_timer_eth56g(9)ice_stop_phy_timer_eth56g(9)ice_start_phy_timer_eth56g(9)ice_check_phy_tx_tstamp_ready_eth56g(9)ice_ptp_read_tx_hwtstamp_status_eth56g(9)ice_ptp_phy_soft_reset_eth56g(9)ice_get_phy_tx_tstamp_ready_eth56g(9)ice_ptp_init_phy_e825(9)ice_fill_phy_msg_e82x(9)ice_is_64b_phy_reg_e82x(9)ice_is_40b_phy_reg_e82x(9)ice_read_phy_reg_e82x(9)ice_read_64b_phy_reg_e82x(9)ice_write_phy_reg_e82x(9)ice_write_40b_phy_reg_e82x(9)ice_write_64b_phy_reg_e82x(9)ice_fill_quad_msg_e82x(9)ice_read_quad_reg_e82x(9)ice_write_quad_reg_e82x(9)ice_read_phy_tstamp_e82x(9)ice_clear_phy_tstamp_e82x(9)ice_ptp_reset_ts_memory_quad_e82x(9)ice_ptp_reset_ts_memory_e82x(9)ice_ptp_set_vernier_wl(9)ice_ptp_init_phc_e82x(9)ice_ptp_prep_phy_time_e82x(9)ice_ptp_prep_port_adj_e82x(9)ice_ptp_prep_phy_adj_e82x(9)ice_ptp_prep_phy_incval_e82x(9)ice_ptp_read_port_capture(9)ice_ptp_write_port_cmd_e82x(9)ice_phy_get_speed_and_fec_e82x(9)ice_phy_cfg_uix_e82x(9)ice_phy_cfg_parpcs_e82x(9)ice_calc_fixed_tx_offset_e82x(9)ice_phy_cfg_tx_offset_e82x(9)ice_phy_calc_pmd_adj_e82x(9)ice_calc_fixed_rx_offset_e82x(9)ice_phy_cfg_rx_offset_e82x(9)ice_ptp_clear_phy_offset_ready_e82x(9)ice_read_phy_and_phc_time_e82x(9)ice_sync_phy_timer_e82x(9)ice_stop_phy_timer_e82x(9)ice_start_phy_timer_e82x(9)ice_get_phy_tx_tstamp_ready_e82x(9)ice_check_phy_tx_tstamp_ready_e82x(9)ice_phy_cfg_intr_e82x(9)ice_ptp_init_phy_e82x(9)ice_read_phy_reg_e810(9)ice_write_phy_reg_e810(9)ice_read_phy_tstamp_ll_e810(9)ice_read_phy_tstamp_sbq_e810(9)ice_read_phy_tstamp_e810(9)ice_clear_phy_tstamp_e810(9)ice_ptp_init_phc_e810(9)ice_ptp_prep_phy_time_e810(9)ice_ptp_prep_phy_adj_ll_e810(9)ice_ptp_prep_phy_adj_e810(9)ice_ptp_prep_phy_incval_ll_e810(9)ice_ptp_prep_phy_incval_e810(9)ice_ptp_port_cmd_e810(9)ice_get_phy_tx_tstamp_ready_e810(9)ice_check_phy_tx_tstamp_ready_e810(9)ice_read_sma_ctrl(9)ice_write_sma_ctrl(9)ice_ptp_read_sdp_ac(9)ice_ptp_init_phy_e810(9)ice_ptp_init_phc_e830(9)ice_ptp_write_direct_incval_e830(9)ice_ptp_write_direct_phc_time_e830(9)ice_ptp_port_cmd_e830(9)ice_read_phy_tstamp_e830(9)ice_get_phy_tx_tstamp_ready_e830(9)ice_check_phy_tx_tstamp_ready_e830(9)ice_ptp_init_phy_e830(9)ice_ptp_lock(9)ice_ptp_unlock(9)ice_ptp_init_hw(9)ice_ptp_write_port_cmd(9)ice_ptp_one_port_cmd(9)ice_ptp_port_cmd(9)ice_ptp_tmr_cmd(9)ice_ptp_init_time(9)ice_ptp_write_incval(9)ice_ptp_write_incval_locked(9)ice_ptp_adj_clock(9)ice_read_phy_tstamp(9)ice_clear_phy_tstamp(9)ice_get_pf_c827_idx(9)ice_ptp_reset_ts_memory(9)ice_ptp_init_phc(9)ice_get_phy_tx_tstamp_ready(9)ice_check_phy_tx_tstamp_ready(9)ice_cgu_get_pin_desc_e823(9)ice_cgu_get_pin_desc(9)ice_cgu_get_num_pins(9)ice_cgu_get_pin_type(9)ice_cgu_get_pin_freq_supp(9)ice_cgu_get_pin_name(9)ice_get_cgu_state(9)ice_get_cgu_rclk_pin_info(9)ice_cgu_get_output_pin_state_caps(9)
xoxo, source/version: ./drivers/net/ethernet/intel/ice Β· date: October 2026 Β· page: ice_phy_cfg_lane_e82x(9) πβ¨
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms