ice_write_40...y_reg_eth56g(9)

💅 ice_write_40b_phy_reg_eth56g — from the kernel API manual, bestie

okay so this is a page out of the Kernel API Manual (the ice_write_40...y_reg_eth56g(9) one, yes the header got truncated, she's mysterious like that 💅) and honestly? it's giving "tiny function, big responsibility." stay with me.

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✨ NAME ✨

ice_write_40b_phy_reg_eth56g — write a 40b value to the PHY. that's it. that's the whole vibe. 🦋

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🌸 SYNOPSIS 🌸

int ice_write_40b_phy_reg_eth56g (struct ice_hw *hw , u8 port , u16
low_addr , u64 val , enum eth56g_res_type res_type );

look at her go. five args, one job. no notes. 👑

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🎀 ARGUMENTS 🎀

• hw — pointer to the HW struct. the main character, literally. everything gets written through her.
• port — port to write to. which port? this port. 🫶
• low_addr — offset of the low register. the "low" part matters, hold that thought.
• val — the 40b value to write. forty whole bits, not 39, not 41. we stan a specific number.
• res_type — resource type. she decides which resource we're talking to.

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🦋 DESCRIPTION 🦋

okay so here's the whole plot: this function does a vibe check on the caller first — it checks if you've specified a known 40 bit register offset. if you haven't, bestie, it's not doing it, sorry.

but if you have? iconic. it takes the 40b value you handed it and writes it to the two associated registers by splitting it up into two chunks: the lower 8 bits and the upper 32 bits. 8 + 32 = 40, the math is mathing, the girlies are fed. ✨🍓

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🔥 RETURN 🔥

• 0 — success. slay. 💖
• EINVAL — not a 40 bit register. respectfully, wrong address, try again 🙈
• other — failed to write to PHY. not the vibe. 😭

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👑 SEE ALSO 👑

first up, the source file herself:

• Kernel file ./drivers/net/ethernet/intel/ice/ice_ptp_hw.c

and now… the friend group. every single one of them, no cap, in order:

ice_get_ptp_src_clock_index(9), ice_ptp_read_src_incval(9),
ice_ptp_tmr_cmd_to_src_reg(9), ice_ptp_tmr_cmd_to_port_reg(9),
ice_ptp_src_cmd(9), ice_ptp_exec_tmr_cmd(9), ice_ptp_cfg_sync_delay(9),
ice_ptp_init_phc_e825c(9), ice_ptp_get_dest_dev_e825(9),
ice_write_phy_eth56g(9), ice_read_phy_eth56g(9),
ice_get_serdes_ref_sel_e825c(9), ice_phy_res_address_eth56g(9),
ice_write_port_eth56g(9), ice_read_port_eth56g(9),
ice_write_ptp_reg_eth56g(9), ice_write_mac_reg_eth56g(9),
ice_write_xpcs_reg_eth56g(9), ice_read_ptp_reg_eth56g(9),
ice_read_mac_reg_eth56g(9), ice_read_gpcs_reg_eth56g(9),
ice_read_port_mem_eth56g(9), ice_write_port_mem_eth56g(9),
ice_write_quad_ptp_reg_eth56g(9), ice_read_quad_ptp_reg_eth56g(9),
ice_is_64b_phy_reg_eth56g(9), ice_is_40b_phy_reg_eth56g(9),
ice_read_64b_phy_reg_eth56g(9), ice_read_64b_ptp_reg_eth56g(9),
ice_write_40b_ptp_reg_eth56g(9), ice_write_64b_phy_reg_eth56g(9),
ice_write_64b_ptp_reg_eth56g(9), ice_read_ptp_tstamp_eth56g(9),
ice_clear_ptp_tstamp_eth56g(9), ice_ptp_reset_ts_memory_eth56g(9),
ice_ptp_prep_port_time_eth56g(9), ice_ptp_prep_phy_time_eth56g(9),
ice_ptp_prep_port_adj_eth56g(9), ice_ptp_prep_phy_adj_eth56g(9),
ice_ptp_prep_phy_incval_eth56g(9), ice_ptp_read_port_capture_eth56g(9),
ice_ptp_write_port_cmd_eth56g(9), ice_phy_get_speed_eth56g(9),
ice_phy_cfg_parpcs_eth56g(9), ice_phy_cfg_ptp_1step_eth56g(9),
mul_u32_u32_fx_q9(9), add_u32_u32_fx(9), ice_ptp_calc_bitslip_eth56g(9),
ice_ptp_calc_deskew_eth56g(9), ice_phy_set_offsets_eth56g(9),
ice_phy_cfg_mac_eth56g(9), ice_phy_cfg_intr_eth56g(9),
ice_read_phy_and_phc_time_eth56g(9), ice_sync_phy_timer_eth56g(9),
ice_stop_phy_timer_eth56g(9), ice_start_phy_timer_eth56g(9),
ice_check_phy_tx_tstamp_ready_eth56g(9),
ice_ptp_read_tx_hwtstamp_status_eth56g(9),
ice_ptp_phy_soft_reset_eth56g(9), ice_get_phy_tx_tstamp_ready_eth56g(9),
ice_ptp_init_phy_e825(9), ice_fill_phy_msg_e82x(9),
ice_is_64b_phy_reg_e82x(9), ice_is_40b_phy_reg_e82x(9),
ice_read_phy_reg_e82x(9), ice_read_64b_phy_reg_e82x(9),
ice_write_phy_reg_e82x(9), ice_write_40b_phy_reg_e82x(9),
ice_write_64b_phy_reg_e82x(9), ice_fill_quad_msg_e82x(9),
ice_read_quad_reg_e82x(9), ice_write_quad_reg_e82x(9),
ice_read_phy_tstamp_e82x(9), ice_clear_phy_tstamp_e82x(9),
ice_ptp_reset_ts_memory_quad_e82x(9), ice_ptp_reset_ts_memory_e82x(9),
ice_ptp_set_vernier_wl(9), ice_ptp_init_phc_e82x(9),
ice_ptp_prep_phy_time_e82x(9), ice_ptp_prep_port_adj_e82x(9),
ice_ptp_prep_phy_adj_e82x(9), ice_ptp_prep_phy_incval_e82x(9),
ice_ptp_read_port_capture(9), ice_ptp_write_port_cmd_e82x(9),
ice_phy_get_speed_and_fec_e82x(9), ice_phy_cfg_lane_e82x(9),
ice_phy_cfg_uix_e82x(9), ice_phy_cfg_parpcs_e82x(9),
ice_calc_fixed_tx_offset_e82x(9), ice_phy_cfg_tx_offset_e82x(9),
ice_phy_calc_pmd_adj_e82x(9), ice_calc_fixed_rx_offset_e82x(9),
ice_phy_cfg_rx_offset_e82x(9), ice_ptp_clear_phy_offset_ready_e82x(9),
ice_read_phy_and_phc_time_e82x(9), ice_sync_phy_timer_e82x(9),
ice_stop_phy_timer_e82x(9), ice_start_phy_timer_e82x(9),
ice_get_phy_tx_tstamp_ready_e82x(9),
ice_check_phy_tx_tstamp_ready_e82x(9), ice_phy_cfg_intr_e82x(9),
ice_ptp_init_phy_e82x(9), ice_read_phy_reg_e810(9),
ice_write_phy_reg_e810(9), ice_read_phy_tstamp_ll_e810(9),
ice_read_phy_tstamp_sbq_e810(9), ice_read_phy_tstamp_e810(9),
ice_clear_phy_tstamp_e810(9), ice_ptp_init_phc_e810(9),
ice_ptp_prep_phy_time_e810(9), ice_ptp_prep_phy_adj_ll_e810(9),
ice_ptp_prep_phy_adj_e810(9), ice_ptp_prep_phy_incval_ll_e810(9),
ice_ptp_prep_phy_incval_e810(9), ice_ptp_port_cmd_e810(9),
ice_get_phy_tx_tstamp_ready_e810(9),
ice_check_phy_tx_tstamp_ready_e810(9), ice_read_sma_ctrl(9),
ice_write_sma_ctrl(9), ice_ptp_read_sdp_ac(9), ice_ptp_init_phy_e810(9),
ice_ptp_init_phc_e830(9), ice_ptp_write_direct_incval_e830(9),
ice_ptp_write_direct_phc_time_e830(9), ice_ptp_port_cmd_e830(9),
ice_read_phy_tstamp_e830(9), ice_get_phy_tx_tstamp_ready_e830(9),
ice_check_phy_tx_tstamp_ready_e830(9), ice_ptp_init_phy_e830(9),
ice_ptp_lock(9), ice_ptp_unlock(9), ice_ptp_init_hw(9),
ice_ptp_write_port_cmd(9), ice_ptp_one_port_cmd(9), ice_ptp_port_cmd(9),
ice_ptp_tmr_cmd(9), ice_ptp_init_time(9), ice_ptp_write_incval(9),
ice_ptp_write_incval_locked(9), ice_ptp_adj_clock(9),
ice_read_phy_tstamp(9), ice_clear_phy_tstamp(9), ice_get_pf_c827_idx(9),
ice_ptp_reset_ts_memory(9), ice_ptp_init_phc(9),
ice_get_phy_tx_tstamp_ready(9), ice_check_phy_tx_tstamp_ready(9),
ice_cgu_get_pin_desc_e823(9), ice_cgu_get_pin_desc(9),
ice_cgu_get_num_pins(9), ice_cgu_get_pin_type(9),
ice_cgu_get_pin_freq_supp(9), ice_cgu_get_pin_name(9),
ice_get_cgu_state(9), ice_get_cgu_rclk_pin_info(9),
ice_cgu_get_output_pin_state_caps(9)

like I said. a whole friend group. iykyk 💜

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tiny note bestie: if your low_addr isn't a known 40 bit register offset, you get EINVAL and nothing gets written. it's not a crash, it's a boundary. respect her boundaries. 🫶

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and that's the page!! 💖 source/version is ./drivers/net/ethernet/intel/ice, dated October 2026 — mwah, tysm for reading, go write some 40b values, ily, bye!! 🎀✨🦋💅