ice_phy_cfg_uix_e82x(9)

💅 ice_phy_cfg_uix_e82x — straight from the Kernel API Manual, bestie ✨

okay so picture this: it's a kernel function, it's got opinions about clocks, and it's the whole reason your packets get timestamped correctly. her name is ice_phy_cfg_uix_e82x and she's lowkey iconic. let's get into it 🎀

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✨ NAME ✨

ice_phy_cfg_uix_e82x — configure the Serdes UI-to-TU conversion for E822, no cap 💫

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🌸 SYNOPSIS 🌸

int ice_phy_cfg_uix_e82x (struct ice_hw *hw , u8 port );

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🦋 ARGUMENTS 🦋

• hw — pointer to the HW structure. yes she needs the hardware. it's giving "give me the whole world before I do anything" 💅
• port — the port to configure, i.e. which one of the ports we're doing this little conversion dance for

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🔥 DESCRIPTION 🔥

okay so what she actually does: she programs the conversion ratio of the Serdes clock "unit intervals" (UIs) into PHC hardware clock time units (TUs). which is a very fancy way of saying: she figures out how many TUs there are per serdes unit interval, and then she writes that conversion into the UIX registers. periodt ✨

and why do we care?? because this conversion is a whole part of the calibration process — the bit where we work out the additional error of a timestamp compared against the actual real time a packet was transmitted or received. so yeah, she's load-bearing. respect her 😭

the hardware uses the number of TUs per 66 UIs, which gets written to the UIX registers, and she does this for the two main serdes clock rates: the 10G/40G serdes clocks and the 25G/100G serdes clocks. two rates, two conversions, one girlboss 🫶

🧮 how she actually does the math (the receipts)

to calculate the conversion ratio, we use these facts:

a) the clock frequency in Hz (cycles per second) b) the number of TUs per cycle (the increment value of the clock) c) 1 second per 1 billion nanoseconds d) the duration of 66 UIs in nanoseconds

given all of those, we can use the following table to work out what ratios to multiply in order to get the number of TUs per 66 UIs:

cycles |   1 second   | incval (TUs) | nanoseconds
-------+--------------+--------------+------------- second | 1 billion
ns |    cycle     |   66 UIs

(yes the table is a little feral, that's just how it renders, we move 💀)

✖️ the actual equation, and why she's built like this

to perform the multiplication using integers without too much loss of precision, we can take use the following equation:

(freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion)

and the reason we scale up to using 6600 UI instead of 66 is to avoid fractional nanosecond UIs (because 66 UI at 10G/40G is 6.4 ns, aka not a whole number, and we don't do that here 🚫).

also the overflow situation, and she was so real for this: the increment value has a maximum expected range of about 34 bits, while the frequency value is about 29 bits. multiplying those two values shouldn't overflow the 64 bits. but then we have to further multiply them again by the Serdes unit interval duration. and to avoid overflow here, we split the overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and a divide by 390,625,000.

ngl, this does lose some precision — but it avoids miscalculation due to arithmetic overflow, and honestly? worth it. precision loss you can live with, overflow you cannot. 💀

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👑 SEE ALSO 👑

okay bestie, buckle up, because the squad is HUGE. every single one of these, no skips, no cuts, we're doing the whole guest list 💖

first, the kernel file herself:

Kernel file ./drivers/net/ethernet/intel/ice/ice_ptp_hw.c

and now the full roster:

ice_get_ptp_src_clock_index(9), ice_ptp_read_src_incval(9),
ice_ptp_tmr_cmd_to_src_reg(9), ice_ptp_tmr_cmd_to_port_reg(9),
ice_ptp_src_cmd(9), ice_ptp_exec_tmr_cmd(9), ice_ptp_cfg_sync_delay(9),
ice_ptp_init_phc_e825c(9), ice_ptp_get_dest_dev_e825(9),
ice_write_phy_eth56g(9), ice_read_phy_eth56g(9),
ice_get_serdes_ref_sel_e825c(9), ice_phy_res_address_eth56g(9),
ice_write_port_eth56g(9), ice_read_port_eth56g(9),
ice_write_ptp_reg_eth56g(9), ice_write_mac_reg_eth56g(9),
ice_write_xpcs_reg_eth56g(9), ice_read_ptp_reg_eth56g(9),
ice_read_mac_reg_eth56g(9), ice_read_gpcs_reg_eth56g(9),
ice_read_port_mem_eth56g(9), ice_write_port_mem_eth56g(9),
ice_write_quad_ptp_reg_eth56g(9), ice_read_quad_ptp_reg_eth56g(9),
ice_is_64b_phy_reg_eth56g(9), ice_is_40b_phy_reg_eth56g(9),
ice_read_64b_phy_reg_eth56g(9), ice_read_64b_ptp_reg_eth56g(9),
ice_write_40b_phy_reg_eth56g(9), ice_write_40b_ptp_reg_eth56g(9),
ice_write_64b_phy_reg_eth56g(9), ice_write_64b_ptp_reg_eth56g(9),
ice_read_ptp_tstamp_eth56g(9), ice_clear_ptp_tstamp_eth56g(9),
ice_ptp_reset_ts_memory_eth56g(9), ice_ptp_prep_port_time_eth56g(9),
ice_ptp_prep_phy_time_eth56g(9), ice_ptp_prep_port_adj_eth56g(9),
ice_ptp_prep_phy_adj_eth56g(9), ice_ptp_prep_phy_incval_eth56g(9),
ice_ptp_read_port_capture_eth56g(9), ice_ptp_write_port_cmd_eth56g(9),
ice_phy_get_speed_eth56g(9), ice_phy_cfg_parpcs_eth56g(9),
ice_phy_cfg_ptp_1step_eth56g(9), mul_u32_u32_fx_q9(9),
add_u32_u32_fx(9), ice_ptp_calc_bitslip_eth56g(9),
ice_ptp_calc_deskew_eth56g(9), ice_phy_set_offsets_eth56g(9),
ice_phy_cfg_mac_eth56g(9), ice_phy_cfg_intr_eth56g(9),
ice_read_phy_and_phc_time_eth56g(9), ice_sync_phy_timer_eth56g(9),
ice_stop_phy_timer_eth56g(9), ice_start_phy_timer_eth56g(9),
ice_check_phy_tx_tstamp_ready_eth56g(9),
ice_ptp_read_tx_hwtstamp_status_eth56g(9),
ice_ptp_phy_soft_reset_eth56g(9), ice_get_phy_tx_tstamp_ready_eth56g(9),
ice_ptp_init_phy_e825(9), ice_fill_phy_msg_e82x(9),
ice_is_64b_phy_reg_e82x(9), ice_is_40b_phy_reg_e82x(9),
ice_read_phy_reg_e82x(9), ice_read_64b_phy_reg_e82x(9),
ice_write_phy_reg_e82x(9), ice_write_40b_phy_reg_e82x(9),
ice_write_64b_phy_reg_e82x(9), ice_fill_quad_msg_e82x(9),
ice_read_quad_reg_e82x(9), ice_write_quad_reg_e82x(9),
ice_read_phy_tstamp_e82x(9), ice_clear_phy_tstamp_e82x(9),
ice_ptp_reset_ts_memory_quad_e82x(9), ice_ptp_reset_ts_memory_e82x(9),
ice_ptp_set_vernier_wl(9), ice_ptp_init_phc_e82x(9),
ice_ptp_prep_phy_time_e82x(9), ice_ptp_prep_port_adj_e82x(9),
ice_ptp_prep_phy_adj_e82x(9), ice_ptp_prep_phy_incval_e82x(9),
ice_ptp_read_port_capture(9), ice_ptp_write_port_cmd_e82x(9),
ice_phy_get_speed_and_fec_e82x(9), ice_phy_cfg_lane_e82x(9),
ice_phy_cfg_parpcs_e82x(9), ice_calc_fixed_tx_offset_e82x(9),
ice_phy_cfg_tx_offset_e82x(9), ice_phy_calc_pmd_adj_e82x(9),
ice_calc_fixed_rx_offset_e82x(9), ice_phy_cfg_rx_offset_e82x(9),
ice_ptp_clear_phy_offset_ready_e82x(9),
ice_read_phy_and_phc_time_e82x(9), ice_sync_phy_timer_e82x(9),
ice_stop_phy_timer_e82x(9), ice_start_phy_timer_e82x(9),
ice_get_phy_tx_tstamp_ready_e82x(9),
ice_check_phy_tx_tstamp_ready_e82x(9), ice_phy_cfg_intr_e82x(9),
ice_ptp_init_phy_e82x(9), ice_read_phy_reg_e810(9),
ice_write_phy_reg_e810(9), ice_read_phy_tstamp_ll_e810(9),
ice_read_phy_tstamp_sbq_e810(9), ice_read_phy_tstamp_e810(9),
ice_clear_phy_tstamp_e810(9), ice_ptp_init_phc_e810(9),
ice_ptp_prep_phy_time_e810(9), ice_ptp_prep_phy_adj_ll_e810(9),
ice_ptp_prep_phy_adj_e810(9), ice_ptp_prep_phy_incval_ll_e810(9),
ice_ptp_prep_phy_incval_e810(9), ice_ptp_port_cmd_e810(9),
ice_get_phy_tx_tstamp_ready_e810(9),
ice_check_phy_tx_tstamp_ready_e810(9), ice_read_sma_ctrl(9),
ice_write_sma_ctrl(9), ice_ptp_read_sdp_ac(9), ice_ptp_init_phy_e810(9),
ice_ptp_init_phc_e830(9), ice_ptp_write_direct_incval_e830(9),
ice_ptp_write_direct_phc_time_e830(9), ice_ptp_port_cmd_e830(9),
ice_read_phy_tstamp_e830(9), ice_get_phy_tx_tstamp_ready_e830(9),
ice_check_phy_tx_tstamp_ready_e830(9), ice_ptp_init_phy_e830(9),
ice_ptp_lock(9), ice_ptp_unlock(9), ice_ptp_init_hw(9),
ice_ptp_write_port_cmd(9), ice_ptp_one_port_cmd(9), ice_ptp_port_cmd(9),
ice_ptp_tmr_cmd(9), ice_ptp_init_time(9), ice_ptp_write_incval(9),
ice_ptp_write_incval_locked(9), ice_ptp_adj_clock(9),
ice_read_phy_tstamp(9), ice_clear_phy_tstamp(9), ice_get_pf_c827_idx(9),
ice_ptp_reset_ts_memory(9), ice_ptp_init_phc(9),
ice_get_phy_tx_tstamp_ready(9), ice_check_phy_tx_tstamp_ready(9),
ice_cgu_get_pin_desc_e823(9), ice_cgu_get_pin_desc(9),
ice_cgu_get_num_pins(9), ice_cgu_get_pin_type(9),
ice_cgu_get_pin_freq_supp(9), ice_cgu_get_pin_name(9),
ice_get_cgu_state(9), ice_get_cgu_rclk_pin_info(9),
ice_cgu_get_output_pin_state_caps(9)

like, that's the entire friend group and every one of them said "omg tell her I said hi" 🌈

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🧚 sign-off 🧚

this little masterpiece lives in ./drivers/net/ethernet/intel/ice, it's dated October 2026, and it's page ice_phy_cfg_uix_e82x(9) of the Kernel API Manual. go read the source, she ate and left no crumbs 💜✨🍓