ice_read_64b_phy_reg_eth56g(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… ice_read_64b_phy_reg_eth56g β€” the kernel API manual, but make it make sense

okay so bestie, welcome to the glow-up of ice_read_64b_phy_reg_eth56g(9) β€” a function from the kernel API manual and honestly? it's giving "small function, big job" energy. it reads a 64bit value from PHY registers ✨ that's the whole vibe. that's the NAME section. we ate.


✨ SYNOPSIS ✨

here's the signature, copied EXACTLY because we do not edit the source, we only stan it:

int ice_read_64b_phy_reg_eth56g (struct ice_hw *hw , u8 port , u16
low_addr , u64 *val , enum eth56g_res_type res_type );

πŸŽ€ ARGUMENTS πŸŽ€

five args, five little besties, let's go through them one by one:

  • hw β€” pointer to the struct ice_hw, aka the whole hardware situation. very main character.
  • port β€” the PHY port you're reading from. pick your lane πŸ’«
  • low_addr β€” offset of the lower register you're reading from. yes, lower β€” there's a whole upper/lower thing happening, keep reading.
  • val β€” on return, this bad boy holds the contents of the 64bit value from the PHY registers. it's a u64 *, so you get the goods by pointer. iconic behavior.
  • res_type β€” the resource type, typed as enum eth56g_res_type. just tell it which resource you mean πŸ¦‹

🌸 DESCRIPTION 🌸

okay so what actually happens: it checks whether the caller has specified a known 40 bit register offset, and then it reads the two registers associated with a 40bit value and returns it in the val pointer.

that's it. that's the lore. two registers, one 64bit value, one pointer, no cap 🫢


πŸ”₯ RETURN πŸ”₯

what you get back, laid out clean:

  • 0 β€” success. we love a zero. periodt βœ…
  • EINVAL β€” not a 64 bit register. rude, but valid πŸ™ˆ
  • other β€” failed to read from PHY. the vibes were off, something broke 😭

πŸ’œ SEE ALSO πŸ’œ

this list is long β€” like, genuinely enormous, and we are not skipping a single one because every reference matters. the kernel file lives at:

Kernel file ./drivers/net/ethernet/intel/ice/ice_ptp_hw.c

and here's the full squad, in order, exactly as listed:

ice_get_ptp_src_clock_index(9), ice_ptp_read_src_incval(9), ice_ptp_tmr_cmd_to_src_reg(9), ice_ptp_tmr_cmd_to_port_reg(9), ice_ptp_src_cmd(9), ice_ptp_exec_tmr_cmd(9), ice_ptp_cfg_sync_delay(9), ice_ptp_init_phc_e825c(9), ice_ptp_get_dest_dev_e825(9), ice_write_phy_eth56g(9), ice_read_phy_eth56g(9), ice_get_serdes_ref_sel_e825c(9), ice_phy_res_address_eth56g(9), ice_write_port_eth56g(9), ice_read_port_eth56g(9), ice_write_ptp_reg_eth56g(9), ice_write_mac_reg_eth56g(9), ice_write_xpcs_reg_eth56g(9), ice_read_ptp_reg_eth56g(9), ice_read_mac_reg_eth56g(9), ice_read_gpcs_reg_eth56g(9), ice_read_port_mem_eth56g(9), ice_write_port_mem_eth56g(9), ice_write_quad_ptp_reg_eth56g(9), ice_read_quad_ptp_reg_eth56g(9), ice_is_64b_phy_reg_eth56g(9), ice_is_40b_phy_reg_eth56g(9), ice_read_64b_ptp_reg_eth56g(9), ice_write_40b_phy_reg_eth56g(9), ice_write_40b_ptp_reg_eth56g(9), ice_write_64b_phy_reg_eth56g(9), ice_write_64b_ptp_reg_eth56g(9), ice_read_ptp_tstamp_eth56g(9), ice_clear_ptp_tstamp_eth56g(9), ice_ptp_reset_ts_memory_eth56g(9), ice_ptp_prep_port_time_eth56g(9), ice_ptp_prep_phy_time_eth56g(9), ice_ptp_prep_port_adj_eth56g(9), ice_ptp_prep_phy_adj_eth56g(9), ice_ptp_prep_phy_incval_eth56g(9), ice_ptp_read_port_capture_eth56g(9), ice_ptp_write_port_cmd_eth56g(9), ice_phy_get_speed_eth56g(9), ice_phy_cfg_parpcs_eth56g(9), ice_phy_cfg_ptp_1step_eth56g(9), mul_u32_u32_fx_q9(9), add_u32_u32_fx(9), ice_ptp_calc_bitslip_eth56g(9), ice_ptp_calc_deskew_eth56g(9), ice_phy_set_offsets_eth56g(9), ice_phy_cfg_mac_eth56g(9), ice_phy_cfg_intr_eth56g(9), ice_read_phy_and_phc_time_eth56g(9), ice_sync_phy_timer_eth56g(9), ice_stop_phy_timer_eth56g(9), ice_start_phy_timer_eth56g(9), ice_check_phy_tx_tstamp_ready_eth56g(9), ice_ptp_read_tx_hwtstamp_status_eth56g(9), ice_ptp_phy_soft_reset_eth56g(9), ice_get_phy_tx_tstamp_ready_eth56g(9), ice_ptp_init_phy_e825(9), ice_fill_phy_msg_e82x(9), ice_is_64b_phy_reg_e82x(9), ice_is_40b_phy_reg_e82x(9), ice_read_phy_reg_e82x(9), ice_read_64b_phy_reg_e82x(9), ice_write_phy_reg_e82x(9), ice_write_40b_phy_reg_e82x(9), ice_write_64b_phy_reg_e82x(9), ice_fill_quad_msg_e82x(9), ice_read_quad_reg_e82x(9), ice_write_quad_reg_e82x(9), ice_read_phy_tstamp_e82x(9), ice_clear_phy_tstamp_e82x(9), ice_ptp_reset_ts_memory_quad_e82x(9), ice_ptp_reset_ts_memory_e82x(9), ice_ptp_set_vernier_wl(9), ice_ptp_init_phc_e82x(9), ice_ptp_prep_phy_time_e82x(9), ice_ptp_prep_port_adj_e82x(9), ice_ptp_prep_phy_adj_e82x(9), ice_ptp_prep_phy_incval_e82x(9), ice_ptp_read_port_capture(9), ice_ptp_write_port_cmd_e82x(9), ice_phy_get_speed_and_fec_e82x(9), ice_phy_cfg_lane_e82x(9), ice_phy_cfg_uix_e82x(9), ice_phy_cfg_parpcs_e82x(9), ice_calc_fixed_tx_offset_e82x(9), ice_phy_cfg_tx_offset_e82x(9), ice_phy_calc_pmd_adj_e82x(9), ice_calc_fixed_rx_offset_e82x(9), ice_phy_cfg_rx_offset_e82x(9), ice_ptp_clear_phy_offset_ready_e82x(9), ice_read_phy_and_phc_time_e82x(9), ice_sync_phy_timer_e82x(9), ice_stop_phy_timer_e82x(9), ice_start_phy_timer_e82x(9), ice_get_phy_tx_tstamp_ready_e82x(9), ice_check_phy_tx_tstamp_ready_e82x(9), ice_phy_cfg_intr_e82x(9), ice_ptp_init_phy_e82x(9), ice_read_phy_reg_e810(9), ice_write_phy_reg_e810(9), ice_read_phy_tstamp_ll_e810(9), ice_read_phy_tstamp_sbq_e810(9), ice_read_phy_tstamp_e810(9), ice_clear_phy_tstamp_e810(9), ice_ptp_init_phc_e810(9), ice_ptp_prep_phy_time_e810(9), ice_ptp_prep_phy_adj_ll_e810(9), ice_ptp_prep_phy_adj_e810(9), ice_ptp_prep_phy_incval_ll_e810(9), ice_ptp_prep_phy_incval_e810(9), ice_ptp_port_cmd_e810(9), ice_get_phy_tx_tstamp_ready_e810(9), ice_check_phy_tx_tstamp_ready_e810(9), ice_read_sma_ctrl(9), ice_write_sma_ctrl(9), ice_ptp_read_sdp_ac(9), ice_ptp_init_phy_e810(9), ice_ptp_init_phc_e830(9), ice_ptp_write_direct_incval_e830(9), ice_ptp_write_direct_phc_time_e830(9), ice_ptp_port_cmd_e830(9), ice_read_phy_tstamp_e830(9), ice_get_phy_tx_tstamp_ready_e830(9), ice_check_phy_tx_tstamp_ready_e830(9), ice_ptp_init_phy_e830(9), ice_ptp_lock(9), ice_ptp_unlock(9), ice_ptp_init_hw(9), ice_ptp_write_port_cmd(9), ice_ptp_one_port_cmd(9), ice_ptp_port_cmd(9), ice_ptp_tmr_cmd(9), ice_ptp_init_time(9), ice_ptp_write_incval(9), ice_ptp_write_incval_locked(9), ice_ptp_adj_clock(9), ice_read_phy_tstamp(9), ice_clear_phy_tstamp(9), ice_get_pf_c827_idx(9), ice_ptp_reset_ts_memory(9), ice_ptp_init_phc(9), ice_get_phy_tx_tstamp_ready(9), ice_check_phy_tx_tstamp_ready(9), ice_cgu_get_pin_desc_e823(9), ice_cgu_get_pin_desc(9), ice_cgu_get_num_pins(9), ice_cgu_get_pin_type(9), ice_cgu_get_pin_freq_supp(9), ice_cgu_get_pin_name(9), ice_get_cgu_state(9), ice_get_cgu_rclk_pin_info(9), ice_cgu_get_output_pin_state_caps(9)

like… that's 150+ references and every single one made the cut πŸ’… no cuts, no edits, no "etc." β€” we keep the whole roster.


and that's the page, bestie 🧚 source lives in ./drivers/net/ethernet/intel/ice, dated October 2026, and the manual page is ice_read_64b_phy_reg_eth56g(9). go read some PHY registers, slay, hydrate, and don't forget your upper and lower halves πŸ’–βœ¨

πŸ“¦ where this page comes from