section 9 · Kernel routines 🧠

87928 pages · page 439 of 440

all 9 (85608)9freebsd (2304)9lua (4)9p (12)

Z (continued)

zstd_min_clevel(9)minimum allowed compression level✨
zstd_reset_cstream(9)reset the context using parameters from creation✨
zstd_reset_dstream(9)reset the context using parameters from creation✨
zswap_load(9)load a folio from zswap✨
zynq_cpu_die(9)Let a CPU core die✨
zynq_early_slcr_init(9)Early slcr init function✨
zynq_get_dtype(9)Return the controller memory width.✨
zynq_get_error_info(9)Get the current ECC error info.✨
zynq_get_mtype(9)Return the controller memory type.✨
zynq_get_revision(9)Get Zynq silicon revision✨
zynq_gpio_dir_in(9)Set the direction of the specified GPIO pin as input✨
zynq_gpio_dir_out(9)Set the direction of the specified GPIO pin as output✨
zynq_gpio_get_bank_pin(9)Get the bank number and pin number within that bank for a given pin in the GPIO device✨
zynq_gpio_get_direction(9)Read the direction of the specified GPIO pin✨
zynq_gpio_get_value(9)Get the state of the specified pin of GPIO device✨
zynq_gpio_irq_ack(9)Acknowledge the interrupt of a gpio pin✨
zynq_gpio_irq_enable(9)Enable the interrupts for a gpio pin✨
zynq_gpio_irq_mask(9)Disable the interrupts for a gpio pin✨
zynq_gpio_irq_unmask(9)Enable the interrupts for a gpio pin✨
zynq_gpio_irqhandler(9)IRQ handler for the gpio banks of a gpio device✨
zynq_gpio_is_zynq(9)test if HW is zynq or zynqmp✨
zynq_gpio_probe(9)Initialization method for a zynq_gpio device✨
zynq_gpio_remove(9)Driver removal function✨
zynq_gpio_set_irq_type(9)Set the irq type for a gpio pin✨
zynq_gpio_set_value(9)Modify the state of the pin with specified value✨
zynq_init_machine(9)System specific initialization, intended to be called from board specific initialization.✨
zynq_map_io(9)Create memory mappings needed for early I/O.✨
zynq_memory_init(9)Initialize special memory✨
zynq_pll_determine_rate(9)Round a clock frequency✨
zynq_pll_disable(9)Disable clock✨
zynq_pll_enable(9)Enable clock✨
zynq_pll_is_enabled(9)Check if a clock is enabled✨
zynq_pll_recalc_rate(9)Recalculate clock frequency✨
zynq_pm_ioremap(9)Create IO mappings✨
zynq_pm_late_init(9)Power management init✨
zynq_qspi_chipselect(9)Select or deselect the chip select line✨
zynq_qspi_config_op(9)Configure QSPI controller for specified transfer✨
zynq_qspi_exec_mem_op(9)Initiates the QSPI transfer✨
zynq_qspi_init_hw(9)Initialize the hardware✨
zynq_qspi_irq(9)Interrupt service routine of the QSPI controller✨
zynq_qspi_probe(9)Probe method for the QSPI driver✨
zynq_qspi_read_op(9)Drains the RX FIFO by as many bytes as possible✨
zynq_qspi_remove(9)Remove method for the QSPI driver✨
zynq_qspi_rxfifo_op(9)Read 1..4 bytes from RxFIFO to RX buffer✨
zynq_qspi_setup_op(9)Configure the QSPI controller✨
zynq_qspi_txfifo_op(9)Write 1..4 bytes from TX buffer to TxFIFO✨
zynq_qspi_write_op(9)Fills the TX FIFO with as many bytes as possible✨
zynq_secondary_init(9)Initialize secondary CPU cores✨
zynq_slcr_cpu_start(9)Start cpu✨
zynq_slcr_cpu_state_read(9)Read cpu state✨
zynq_slcr_cpu_state_write(9)Write cpu state✨
zynq_slcr_cpu_stop(9)Stop cpu✨
zynq_slcr_get_device_id(9)Read device code id✨
zynq_slcr_read(9)Read a register in SLCR block✨
zynq_slcr_system_restart(9)Restart the entire system.✨
zynq_slcr_unlock(9)Unlock SLCR registers✨
zynq_slcr_write(9)Write to a register in SLCR block✨
zynqmp_clear_pm_state(9)Clear subsystem state✨
zynqmp_clk_divider_determine_rate(9)Determine rate of divider clock✨
zynqmp_clk_divider_recalc_rate(9)Recalc rate of divider clock✨
zynqmp_clk_divider_set_rate(9)Set rate of divider clock✨
zynqmp_clk_gate_enable(9)Enable clock✨
zynqmp_clk_gate_is_enabled(9)Check clock state✨
zynqmp_clk_get_max_divisor(9)Get maximum supported divisor from firmware.✨
zynqmp_clk_mux_get_parent(9)Get parent of clock✨
zynqmp_clk_mux_set_parent(9)Set parent of clock✨
zynqmp_clk_register_divider(9)Register a divider clock✨
zynqmp_clk_register_fixed_factor(9)Register fixed factor with the clock framework✨
zynqmp_clk_register_gate(9)Register a gate clock with the clock framework✨
zynqmp_clk_register_mux(9)Register a mux table with the clock framework✨
zynqmp_clk_register_pll(9)Register PLL with the clock framework✨
zynqmp_clk_setup(9)Setup the clock framework and register clocks✨
zynqmp_clock_get_parents(9)Get parents info from firmware using PM_API✨
zynqmp_clock_get_topology(9)Get topology of clock from firmware using PM_API✨
zynqmp_disp_avbuf_disable(9)Disable the video pipe✨
zynqmp_disp_avbuf_disable_audio(9)Disable audio✨
zynqmp_disp_avbuf_disable_channels(9)Disable buffer channels✨
zynqmp_disp_avbuf_disable_video(9)Disable a video layer✨
zynqmp_disp_avbuf_enable(9)Enable the video pipe✨
zynqmp_disp_avbuf_enable_audio(9)Enable audio✨
zynqmp_disp_avbuf_enable_channels(9)Enable buffer channels✨
zynqmp_disp_avbuf_enable_video(9)Enable a video layer✨
zynqmp_disp_avbuf_set_clocks_sources(9)Set the clocks sources✨
zynqmp_disp_avbuf_set_format(9)Set the input format for a layer✨
zynqmp_disp_blend_layer_disable(9)Disable a layer✨
zynqmp_disp_blend_layer_enable(9)Enable a layer✨
zynqmp_disp_blend_layer_set_csc(9)Configure colorspace conversion for layer✨
zynqmp_disp_blend_set_bg_color(9)Set the background color✨
zynqmp_disp_blend_set_global_alpha(9)Configure global alpha blending✨
zynqmp_disp_blend_set_output_format(9)Set the output format of the blender✨
zynqmp_disp_create_layers(9)Create and initialize all layers✨
zynqmp_disp_destroy_layers(9)Destroy all layers✨
zynqmp_disp_disable(9)Disable the display controller✨
zynqmp_disp_enable(9)Enable the display controller✨
zynqmp_disp_layer_disable(9)Disable the layer✨
zynqmp_disp_layer_drm_formats(9)Return the DRM formats supported by the layer✨
zynqmp_disp_layer_enable(9)Enable a layer✨
zynqmp_disp_layer_find_format(9)Find format information for a DRM format✨
zynqmp_disp_layer_find_live_format(9)Find format information for given media bus format✨
zynqmp_disp_layer_release_dma(9)Release DMA channels for a layer✨
zynqmp_disp_layer_request_dma(9)Request DMA channels for a layer✨
zynqmp_disp_layer_set_format(9)Set the layer format✨
zynqmp_disp_layer_set_live_format(9)Set the live video layer format✨
zynqmp_disp_layer_update(9)Update the layer framebuffer✨
zynqmp_disp_live_layer_formats(9)Return the media bus formats supported by the live video layer✨
zynqmp_disp_setup_clock(9)Configure the display controller pixel clock rate✨
zynqmp_dma_alloc_chan_resources(9)Allocate channel resources✨
zynqmp_dma_chan_desc_cleanup(9)Cleanup the completed descriptors✨
zynqmp_dma_chan_probe(9)Per Channel Probing✨
zynqmp_dma_chan_remove(9)Channel remove function✨
zynqmp_dma_complete_descriptor(9)Mark the active descriptor as complete✨
zynqmp_dma_config_sg_ll_desc(9)Configure the linked list descriptor✨
zynqmp_dma_desc_config_eod(9)Mark the descriptor as end descriptor✨
zynqmp_dma_device_config(9)Zynqmp dma device configuration✨
zynqmp_dma_device_terminate_all(9)Aborts all transfers on a channel✨
zynqmp_dma_do_tasklet(9)Schedule completion tasklet✨
zynqmp_dma_free_chan_resources(9)Free channel resources✨
zynqmp_dma_free_desc_list(9)Free descriptors list✨
zynqmp_dma_free_descriptor(9)Issue pending transactions✨
zynqmp_dma_free_descriptors(9)Free channel descriptors✨
zynqmp_dma_get_descriptor(9)Get the sw descriptor from the pool✨
zynqmp_dma_handle_ovfl_int(9)Process the overflow interrupt✨
zynqmp_dma_init(9)Initialize the channel✨
zynqmp_dma_irq_handler(9)ZynqMP DMA Interrupt handler✨
zynqmp_dma_issue_pending(9)Issue pending transactions✨
zynqmp_dma_prep_memcpy(9)prepare descriptors for memcpy transaction✨
zynqmp_dma_probe(9)Driver probe function✨
zynqmp_dma_remove(9)Driver remove function✨
zynqmp_dma_reset(9)Reset the channel✨
zynqmp_dma_resume(9)Resume from suspend✨
zynqmp_dma_runtime_resume(9)Runtime suspend method for the driver✨
zynqmp_dma_runtime_suspend(9)Runtime suspend method for the driver✨
zynqmp_dma_start(9)Start DMA channel✨
zynqmp_dma_start_transfer(9)Initiate the new transfer✨
zynqmp_dma_suspend(9)Suspend method for the driver✨
zynqmp_dma_synchronize(9)Synchronizes the termination of a transfers to the current context.✨
zynqmp_dma_tx_submit(9)Submit DMA transaction✨
zynqmp_dma_update_desc_to_ctrlr(9)Updates descriptor to the controller✨
zynqmp_dp_adjust_train(9)Adjust train values✨
zynqmp_dp_aux_cleanup(9)Cleanup the DP AUX✨
zynqmp_dp_aux_cmd_submit(9)Submit aux command✨
zynqmp_dp_aux_init(9)Initialize and register the DP AUX✨
zynqmp_dp_disable_vblank(9)Disable vblank✨
zynqmp_dp_disp_connected_live_layer(9)Return the first connected live layer✨
zynqmp_dp_enable_vblank(9)Enable vblank✨
zynqmp_dp_encoder_mode_set_stream(9)Configure the main stream✨
zynqmp_dp_encoder_mode_set_transfer_unit(9)Set the transfer unit values✨
zynqmp_dp_link_train_ce(9)Train channel equalization✨
zynqmp_dp_link_train_cr(9)Train clock recovery✨
zynqmp_dp_max_rate(9)Calculate and return available max pixel clock✨
zynqmp_dp_mode_configure(9)Configure the link values✨
zynqmp_dp_phy_exit(9)Exit the phy✨
zynqmp_dp_phy_init(9)Initialize the phy✨
zynqmp_dp_phy_probe(9)Probe the PHYs✨
zynqmp_dp_phy_ready(9)Check if PHY is ready✨
zynqmp_dp_set_format(9)Set the input format✨
zynqmp_dp_set_test_pattern(9)Configure the link for a test pattern✨
zynqmp_dp_setup(9)Set up major link parameters✨
zynqmp_dp_train(9)Train the link✨
zynqmp_dp_train_loop(9)Downshift the link rate during training✨
zynqmp_dp_update_misc(9)Write the misc registers✨
zynqmp_dp_update_vs_emph(9)Update the training values✨
zynqmp_dpsub_drm_handle_vblank(9)Handle the vblank event✨
zynqmp_get_clock_info(9)Get clock information from firmware using PM_API✨
zynqmp_get_clock_name(9)Get name of clock from Clock index✨
zynqmp_get_clock_type(9)Get type of clock✨
zynqmp_get_dtype(9)Return the controller memory width.✨
zynqmp_get_error_info(9)Get the current ECC error info.✨
zynqmp_get_mem_info(9)Get the current memory info.✨
zynqmp_get_mtype(9)Returns controller memory type.✨
zynqmp_get_parent_list(9)Create list of parents name✨
zynqmp_gpd_attach_dev(9)Attach device to the PM domain✨
zynqmp_gpd_detach_dev(9)Detach device from the PM domain✨
zynqmp_gpd_is_active_wakeup_path(9)Check if device is in wakeup source path✨
zynqmp_gpd_power_off(9)Power off PM domain✨
zynqmp_gpd_power_on(9)Power on PM domain✨
zynqmp_gqspi_read(9)For GQSPI controller read operation✨
zynqmp_gqspi_selecttarget(9)For selection of target device✨
zynqmp_gqspi_write(9)For GQSPI controller write operation✨
zynqmp_ipi_free_mboxes(9)Free IPI mailboxes devices✨
zynqmp_ipi_interrupt(9)Interrupt handler for IPI notification✨
zynqmp_ipi_last_tx_done(9)See if the last tx message is sent✨
zynqmp_ipi_mbox_dev_release(9)release the existence of a ipi mbox dev✨
zynqmp_ipi_mbox_get_buf_res(9)Get buffer resource from the IPI dev node✨
zynqmp_ipi_mbox_probe(9)probe IPI mailbox resource from device node✨
zynqmp_ipi_of_xlate(9)Translate of phandle to IPI mailbox channel✨
zynqmp_ipi_peek_data(9)Peek to see if there are any rx messages.✨
zynqmp_ipi_send_data(9)Send data✨
zynqmp_ipi_setup(9)set up IPI Buffers for classic flow✨
zynqmp_ipi_shutdown(9)Shutdown the IPI channel✨
zynqmp_ipi_startup(9)Startup the IPI channel✨
zynqmp_is_valid_clock(9)Check whether clock is valid or not✨
zynqmp_pinconf_cfg_get(9)get config value for the pin✨
zynqmp_pinconf_cfg_set(9)Set requested config for the pin✨
zynqmp_pinconf_group_set(9)Set requested config for the group✨
zynqmp_pinctrl_create_pin_groups(9)assign pins to respective groups✨
zynqmp_pinctrl_prepare_func_groups(9)prepare function and groups data✨
zynqmp_pinctrl_prepare_function_info(9)prepare function info✨
zynqmp_pinctrl_prepare_group_pins(9)prepare each group's pin data✨
zynqmp_pinctrl_prepare_pin_desc(9)prepare pin description info✨