zynqmp_clk_divider_set_rate(9)

✨ NAME ✨

zynqmp_clk_divider_set_rate — set rate of divider clock 💅✨

Okay bestie, this is the Kernel API Manual page for zynqmp_clk_divider_set_rate(9), and it's literally here to set the rate of a divider clock. No cap, that's the whole main-character job. 🎀

📜 SYNOPSIS 📜

int zynqmp_clk_divider_set_rate (struct clk_hw *hw , unsigned long rate , unsigned long parent_rate );

🧚 ARGUMENTS 🧚

• hw — the handle between common and hardware-specific interfaces 🫶
• rate — the rate of the clock that's getting set 🌸
• parent_rate — the rate of the parent clock 👑

🫶 RETURN 🫶

Returns 0 on success; otherwise it's error+reason. That's the whole vibe check. ✅

👑 SEE ALSO 👑

The kernel file is ./drivers/clk/zynqmp/divider.c, and you're gonna want to peek at these icons too:

• struct zynqmp_clk_divider(9)
• zynqmp_clk_divider_recalc_rate(9)
• zynqmp_clk_divider_determine_rate(9)
• zynqmp_clk_get_max_divisor(9)
• zynqmp_clk_register_divider(9)

And that's the tea 🍓: this page is from the Kernel API Manual, lives under ./drivers/clk/zynqmp, and is dated October 2026 — slay, zynqmp_clk_divider_set_rate(9) forever. 💖