zynqmp_dp_link_train_ce(9)

🎀 zynqmp_dp_link_train_ce(9) 🎀

okay bestie, welcome to the Kernel API Manual ✨ this page is zynqmp_dp_link_train_ce(9), and it is literally about training channel equalization. no cap. 💅

🌸 NAME 🌸

zynqmp_dp_link_train_ce — Train channel equalization. That's the whole assignment. Periodt. 💖

✨ SYNOPSIS ✨

int zynqmp_dp_link_train_ce (struct zynqmp_dp *dp );

🧚 ARGUMENTS 🧚

• dp — DisplayPort IP core structure. That's the DisplayPort IP core structure, bestie. 🫶

🔥 RETURN 🔥

Returns 0 if channel equalization train is done successfully, or corresponding error code. So like: success gives you 0, otherwise you get the matching error code. 💀

👑 SEE ALSO 👑

Kernel file ./drivers/gpu/drm/xlnx/zynqmp_dp.c and all the adjacent lore:

• struct zynqmp_dp_link_config(9)
• struct zynqmp_dp_mode(9)
• struct zynqmp_dp_config(9)
• enum test_pattern(9)
• struct zynqmp_dp_test(9)
• struct zynqmp_dp_train_set_priv(9)
• struct zynqmp_dp(9)
• zynqmp_dp_phy_init(9)
• zynqmp_dp_phy_exit(9)
• zynqmp_dp_phy_probe(9)
• zynqmp_dp_phy_ready(9)
• zynqmp_dp_max_rate(9)
• zynqmp_dp_mode_configure(9)
• zynqmp_dp_adjust_train(9)
• zynqmp_dp_update_vs_emph(9)
• zynqmp_dp_link_train_cr(9)
• zynqmp_dp_setup(9)
• zynqmp_dp_train(9)
• zynqmp_dp_train_loop(9)
• zynqmp_dp_aux_cmd_submit(9)
• zynqmp_dp_aux_init(9)
• zynqmp_dp_aux_cleanup(9)
• zynqmp_dp_update_misc(9)
• zynqmp_dp_set_format(9)
• zynqmp_dp_encoder_mode_set_transfer_unit(9)
• zynqmp_dp_encoder_mode_set_stream(9)
• zynqmp_dp_disp_connected_live_layer(9)
• zynqmp_dp_set_test_pattern(9)
• zynqmp_dp_enable_vblank(9)
• zynqmp_dp_disable_vblank(9)

okay that's the whole page, bestie!! cute sign-off time: source/version is ./drivers/gpu/drm/xlnx, date is October 2026, and the page is zynqmp_dp_link_train_ce(9). 💖✨🌸