zynqmp_dp_e...e_set_stream(9)

💖 zynqmp_dp_encoder_mode_set_stream(9) 💖

okay so bestie, this is the Kernel API Manual entry for zynqmp_dp_encoder_mode_set_stream(9) — yes the title is a whole keyboard smash, but we're here and we're slaying 💅✨

🎀 NAME 🎀

zynqmp_dp_encoder_mode_set_stream — Configure the main stream 🦋

✨ SYNOPSIS ✨

void zynqmp_dp_encoder_mode_set_stream (struct zynqmp_dp *dp , const
       struct drm_display_mode *mode );

🌸 ARGUMENTS 🌸

• dp — the DisplayPort IP core structure, aka the main-character struct this call is working with 💜
• mode — the requested display mode. Yes bestie, this is the mode we're configuring for 👑

🌈 DESCRIPTION 🌈

Configure the main stream based on the requested mode mode. The calculation is based on the IP core specification — that's the whole vibe, and it's giving "trust the spec" 😌✨

🦋 SEE ALSO 🦋

Kernel file: ./drivers/gpu/drm/xlnx/zynqmp_dp.c

• struct zynqmp_dp_link_config(9)
• struct zynqmp_dp_mode(9)
• struct zynqmp_dp_config(9)
• enum test_pattern(9)
• struct zynqmp_dp_test(9)
• struct zynqmp_dp_train_set_priv(9)
• struct zynqmp_dp(9)
• zynqmp_dp_phy_init(9)
• zynqmp_dp_phy_exit(9)
• zynqmp_dp_phy_probe(9)
• zynqmp_dp_phy_ready(9)
• zynqmp_dp_max_rate(9)
• zynqmp_dp_mode_configure(9)
• zynqmp_dp_adjust_train(9)
• zynqmp_dp_update_vs_emph(9)
• zynqmp_dp_link_train_cr(9)
• zynqmp_dp_link_train_ce(9)
• zynqmp_dp_setup(9)
• zynqmp_dp_train(9)
• zynqmp_dp_train_loop(9)
• zynqmp_dp_aux_cmd_submit(9)
• zynqmp_dp_aux_init(9)
• zynqmp_dp_aux_cleanup(9)
• zynqmp_dp_update_misc(9)
• zynqmp_dp_set_format(9)
• zynqmp_dp_encoder_mode_set_transfer_unit(9)
• zynqmp_dp_disp_connected_live_layer(9)
• zynqmp_dp_set_test_pattern(9)
• zynqmp_dp_enable_vblank(9)
• zynqmp_dp_disable_vblank(9)

omg before you go: this page's source/version is ./drivers/gpu/drm/xlnx, and it's dated October 2026 — bye bestie, go configure that main stream 💅✨🫶