section 9 · Kernel routines 🧠

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intel_digital_connector_atomic_get_property(9)hook for connector->atomic_get_property.✨
intel_digital_connector_atomic_set_property(9)hook for connector->atomic_set_property.✨
intel_digital_connector_duplicate_state(9)duplicate connector state✨
intel_display_driver_check_access(9)Check if the current thread has disaplay HW access✨
intel_display_driver_disable_user_access(9)Disable display HW access for user threads✨
intel_display_driver_enable_user_access(9)Enable display HW access for all threads✨
intel_display_driver_resume_access(9)Resume display HW access for the resume thread✨
intel_display_driver_suspend_access(9)Suspend display HW access for all threads✨
INTEL_DISPLAY_MEMBER_STATIC_ASSERT(9)ensure correct placing of drm and display members✨
intel_display_params_dump(9)dump intel display modparams✨
intel_display_power_cleanup(9)clean up power domains resources✨
intel_display_power_disable(9)disable toggling of display power wells✨
intel_display_power_driver_remove(9)deinitialize hw power domain state✨
intel_display_power_enable(9)enable toggling of display power wells✨
intel_display_power_flush_work(9)flushes the async display power disabling work✨
intel_display_power_flush_work_sync(9)flushes and syncs the async display power disabling work✨
intel_display_power_get(9)grab a power domain reference✨
intel_display_power_get_current_dc_state(9)Set target dc state.✨
intel_display_power_get_if_enabled(9)grab a reference for an enabled display power domain✨
intel_display_power_init(9)initializes the power domain structures✨
intel_display_power_init_hw(9)initialize hardware power domain state✨
intel_display_power_is_enabled(9)check for a power domain✨
intel_display_power_map_cleanup(9)clean up power domain -> power well mappings✨
intel_display_power_map_init(9)initialize power domain -> power well mappings✨
intel_display_power_put(9)release a power domain reference✨
intel_display_power_put_unchecked(9)release an unchecked power domain reference✨
intel_display_power_sanitize_state(9)sanitize power domains state✨
intel_display_power_set_target_dc_state(9)Set target dc state.✨
intel_dkl_phy_init(9)initialize Dekel PHY✨
intel_dkl_phy_posting_read(9)do a posting read from a Dekel PHY register✨
intel_dkl_phy_read(9)read a Dekel PHY register✨
intel_dkl_phy_rmw(9)read-modify-write a Dekel PHY register✨
intel_dkl_phy_write(9)write a Dekel PHY register✨
intel_dmc_block_pkgc(9)block PKG C-state✨
intel_dmc_disable_program(9)disable the firmware✨
intel_dmc_fini(9)unload the DMC firmware.✨
intel_dmc_init(9)initialize the firmware loading.✨
intel_dmc_load_program(9)write the firmware from memory to register.✨
intel_dmc_resume(9)init DMC firmware during system resume✨
intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(9)start of PKG C- state exit✨
intel_dmc_suspend(9)prepare DMC firmware before system suspend✨
intel_dp_check_mst_status(9)service any pending MST interrupts, check link status✨
intel_dp_effective_data_rate(9)Return the pixel data rate accounting for BW allocation overhead✨
intel_dp_init_lttpr_and_dprx_caps(9)detect LTTPR and DPRX caps, init the LTTPR link training mode✨
intel_dp_is_edp(9)is the given port attached to an eDP panel (either CPU or PCH)✨
intel_dp_link_caps_debugfs_add(9)add link caps debugfs files for a connector✨
intel_dp_link_caps_disable_config(9)disable a configuration✨
intel_dp_link_caps_get_max_bw_config(9)get maximum BW link configuration✨
intel_dp_link_caps_get_max_config(9)get the maximum config in a given order✨
intel_dp_link_caps_get_max_limits(9)get the current maximum link limits✨
intel_dp_link_caps_reset(9)reset link capability restrictions✨
intel_dp_link_caps_reset_max_limits(9)reset the current maximum link limits✨
intel_dp_link_caps_set_max_limits(9)set the current maximum link limits✨
intel_dp_link_caps_update(9)rebuild the supported link configuration state✨
intel_dp_link_symbol_clock(9)convert link rate to link symbol clock✨
intel_dp_link_symbol_size(9)get the link symbol size for a given link rate✨
intel_dp_max_link_data_rate(9)Calculate the maximum rate for the given link params✨
intel_dp_mst_add_topology_state_for_connector(9)add MST topology state for a connector✨
intel_dp_mst_add_topology_state_for_crtc(9)add MST topology state for a CRTC✨
intel_dp_mst_atomic_check_link(9)check all modeset MST link configuration✨
intel_dp_mst_crtc_needs_modeset(9)check if changes in topology need to modeset the given CRTC✨
intel_dp_mst_prepare_probe(9)Prepare an MST link for topology probing✨
intel_dp_sink_disable_decompression(9)Disable DSC decompression in sink/last branch device✨
intel_dp_sink_enable_decompression(9)Enable DSC decompression in sink/last branch device✨
intel_dp_start_link_train(9)start link training✨
intel_dp_stop_link_train(9)stop link training✨
intel_dp_sync_state(9)sync the encoder state during init/resume✨
intel_dp_tunnel_atomic_add_state_for_crtc(9)Add CRTC specific DP tunnel state✨
intel_dp_tunnel_atomic_alloc_bw(9)Allocate the BW for all modeset tunnels✨
intel_dp_tunnel_atomic_check_link(9)Check the DP tunnel atomic state✨
intel_dp_tunnel_atomic_check_state(9)Check a connector's DP tunnel specific state✨
intel_dp_tunnel_atomic_cleanup_inherited_state(9)Free any inherited DP tunnel state✨
intel_dp_tunnel_atomic_clear_stream_bw(9)Clear any DP tunnel stream BW requirement✨
intel_dp_tunnel_atomic_compute_stream_bw(9)Compute the BW required by a DP tunnel stream✨
intel_dp_tunnel_bw_alloc_is_enabled(9)Query the BW allocation support on a tunnel✨
intel_dp_tunnel_destroy(9)Destroy a DP tunnel✨
intel_dp_tunnel_detect(9)Detect a DP tunnel on a port✨
intel_dp_tunnel_disconnect(9)Disconnect a DP tunnel from a port✨
intel_dp_tunnel_mgr_cleanup(9)Clean up the DP tunnel manager state✨
intel_dp_tunnel_mgr_init(9)Initialize the DP tunnel manager✨
intel_dp_tunnel_pr_optimization_supported(9)Query the PR BW optimization support✨
intel_dp_tunnel_resume(9)Resume a DP tunnel connected on a port✨
intel_dp_tunnel_suspend(9)Suspend a DP tunnel connected on a port✨
intel_dpll_compare_hw_state(9)compare the two states✨
intel_dpll_compute(9)compute DPLL state CRTC and encoder combination✨
intel_dpll_crtc_get(9)Get a DPLL reference for a CRTC✨
intel_dpll_crtc_put(9)Drop a DPLL reference for a CRTC✨
intel_dpll_disable(9)disable a CRTC's shared DPLL✨
intel_dpll_dump_hw_state(9)dump hw_state✨
intel_dpll_enable(9)enable a CRTC's DPLL✨
intel_dpll_get_freq(9)calculate the DPLL's output frequency✨
intel_dpll_get_hw_state(9)readout the DPLL's hardware state✨
intel_dpll_init(9)Initialize DPLLs✨
intel_dpll_release(9)end use of DPLLs by CRTC in atomic state✨
intel_dpll_reserve(9)reserve DPLLs for CRTC and encoder combination✨
intel_dpll_swap_state(9)make atomic DPLL configuration effective✨
intel_dpll_update_active(9)update the active DPLL for a CRTC/encoder✨
intel_dpt_resume(9)restore the memory mapping for all DPT FBs during system resume✨
intel_dpt_suspend(9)suspend the memory mapping for all DPT FBs during system suspend✨
intel_drrs_activate(9)activate DRRS✨
intel_drrs_crtc_init(9)Init DRRS for CRTC✨
intel_drrs_deactivate(9)deactivate DRRS✨
intel_drrs_flush(9)Restart Idleness DRRS✨
intel_drrs_invalidate(9)Disable Idleness DRRS✨
intel_dsb_cleanup(9)To cleanup DSB context.✨
intel_dsb_commit(9)Trigger workload execution of DSB.✨
intel_dsb_prepare(9)Allocate, pin and map the DSB command buffer.✨
intel_dsb_reg_write_indexed(9)Emit indexed register write to the DSB context✨
intel_engine_cleanup_cmd_parser(9)clean up cmd parser related fields✨
intel_engine_cleanup_common(9)cleans up the engine state created by the common initializers.✨
intel_engine_cmd_parser(9)parse a batch buffer for privilege violations✨
intel_engine_context_size(9)return the size of the context for an engine✨
intel_engine_get_busy_time(9)Return current accumulated engine busyness✨
intel_engine_init_cmd_parser(9)set cmd parser related fields for an engine✨
intel_engine_is_idle(9)Report if the engine has finished process all work✨
intel_engine_reset(9)reset GPU engine to recover from a hang✨
intel_engine_reset_pinned_contexts(9)Reset the pinned contexts of an engine.✨
intel_engine_resume(9)re-initializes the HW state of the engine✨
intel_engines_init_mmio(9)allocate and prepare the Engine Command Streamers✨
intel_engines_release(9)free the resources allocated for Command Streamers✨
intel_eth_pci_probe(9)✨
intel_eth_pci_remove(9)✨
intel_fb_get_format_info(9)Get a modifier specific format information✨
intel_fb_is_ccs_aux_plane(9)Check if a framebuffer color plane is a CCS AUX plane✨
intel_fb_is_ccs_modifier(9)Check if a modifier is a CCS modifier type✨
intel_fb_is_gen12_ccs_aux_plane(9)Check if a framebuffer color plane is a GEN12 CCS AUX plane✨
intel_fb_is_mc_ccs_modifier(9)Check if a modifier is an MC CCS modifier type✨
intel_fb_is_rc_ccs_cc_modifier(9)Check if a modifier is an RC CCS CC modifier type✨
intel_fb_is_tile4_modifier(9)Check if a modifier is a tile4 modifier type✨
intel_fb_is_tiled_modifier(9)Check if a modifier is a tiled modifier type✨
intel_fb_needs_64k_phys(9)Check if modifier requires 64k physical placement.✨
intel_fb_plane_get_modifiers(9)Get the modifiers for the given platform and plane capabilities✨
intel_fb_plane_supports_modifier(9)Determine if a modifier is supported by the given plane✨
intel_fb_rc_ccs_cc_plane(9)Get the CCS CC color plane index for a framebuffer✨
intel_fbc_disable(9)disable FBC if it's associated with crtc✨
intel_fbc_handle_fifo_underrun_irq(9)disable FBC when we get a FIFO underrun✨
intel_fbc_init(9)Initialize FBC✨
intel_fbc_read_underrun_dbg_info(9)Read and log FBC-related FIFO underrun debug info✨
intel_fbc_sanitize(9)Sanitize FBC✨
intel_fdi_add_affected_crtcs(9)add CRTCs on FDI affected by other modeset CRTCs✨
intel_fdi_atomic_check_link(9)check all modeset FDI link configuration✨
intel_format_info_is_yuv_semiplanar(9)Check if the given format is YUV semiplanar✨
intel_frontbuffer_flip(9)synchronous frontbuffer flip✨
intel_frontbuffer_flush(9)flush frontbuffer object✨
intel_frontbuffer_invalidate(9)invalidate frontbuffer object✨
intel_frontbuffer_queue_flush(9)queue flushing frontbuffer object✨
intel_frontbuffer_track(9)update frontbuffer tracking✨
intel_get_dpll_by_id(9)get a DPLL given its id✨
intel_ggtt_restore_fences(9)restore fence state✨
intel_gmbus_setup(9)instantiate all Intel i2c GMBuses✨
intel_gpio_add_pin_ranges(9)add GPIO pin ranges for all groups in all communities✨
intel_gpio_to_pin(9)Translate from GPIO offset to pin number✨
intel_gt_bind_context_set_ready(9)Set the context binding as ready✨
intel_gt_bind_context_set_unready(9)Set the context binding as ready✨
intel_gt_handle_error(9)handle a gpu error✨
intel_gt_is_bind_context_ready(9)Check if context binding is ready✨
intel_gt_mcr_get_nonterminated_steering(9)find group/instance values that will steer a register to a non-terminated instance✨
intel_gt_mcr_get_ss_steering(9)returns the group/instance steering for a SS✨
intel_gt_mcr_lock(9)Acquire MCR steering lock✨
intel_gt_mcr_lock_sanitize(9)Sanitize MCR steering lock✨
intel_gt_mcr_multicast_rmw(9)Performs a multicast RMW operations✨
intel_gt_mcr_multicast_write(9)write a value to all instances of an MCR register✨
intel_gt_mcr_multicast_write_fw(9)write a value to all instances of an MCR register✨
intel_gt_mcr_read(9)read a specific instance of an MCR register✨
intel_gt_mcr_read_any(9)reads one instance of an MCR register✨
intel_gt_mcr_read_any_fw(9)reads one instance of an MCR register✨
intel_gt_mcr_unicast_write(9)write a specific instance of an MCR register✨
intel_gt_mcr_unlock(9)Release MCR steering lock✨
intel_gt_mcr_wait_for_reg(9)wait until MCR register matches expected state✨
intel_gt_reset(9)reset chip after a hang✨
intel_gt_reset_all_engines(9)Reset all engines in the given gt.✨
intel_gt_reset_engine(9)Reset a specific engine within a gt.✨
intel_guc_ads_create(9)allocates and initializes GuC ADS.✨
intel_guc_ads_reset(9)prepares GuC Additional Data Struct for reuse✨
intel_guc_allocate_and_map_vma(9)Allocate and map VMA for GuC usage✨
intel_guc_allocate_vma(9)Allocate a GGTT VMA for GuC usage✨
intel_guc_auth_huc(9)Send action to GuC to authenticate HuC ucode✨
intel_guc_ct_disable(9)Disable buffer based command transport.✨
intel_guc_ct_enable(9)Enable buffer based command transport.✨
intel_guc_ct_fini(9)Fini buffer-based communication✨
intel_guc_ct_init(9)Init buffer-based communication✨
intel_guc_ct_init_early(9)Initialize CT state without requiring device access✨
intel_guc_fw_upload(9)load GuC uCode to device✨
intel_guc_ggtt_offset(9)Get and validate the GGTT offset of @vma✨
intel_guc_load_status(9)dump information about GuC load status✨
intel_guc_log_dump(9)dump the contents of the GuC log✨
intel_guc_log_info(9)dump information about GuC log relay✨
intel_guc_resume(9)notify GuC resuming from suspend state✨
intel_guc_slpc_get_max_freq(9)Get max frequency limit for SLPC.✨
intel_guc_slpc_get_min_freq(9)Get min frequency limit for SLPC.✨
intel_guc_slpc_set_max_freq(9)Set max frequency limit for SLPC.✨
intel_guc_slpc_set_min_freq(9)Set min frequency limit for SLPC.✨
intel_guc_suspend(9)notify GuC entering suspend state✨
intel_gvt_activate_vgpu(9)activate a virtual GPU✨
intel_gvt_clean_device(9)clean a GVT device✨
intel_gvt_clean_gtt(9)clean up mm components of a GVT device✨
intel_gvt_clean_mmio_info(9)clean up MMIO information table for GVT device✨
intel_gvt_create_idle_vgpu(9)create an idle virtual GPU✨
intel_gvt_deactivate_vgpu(9)deactivate a virtual GPU✨
intel_gvt_debugfs_add_vgpu(9)register debugfs entries for a vGPU✨