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S (continued)

start_userspace(9)prepare a new userspace process✨
start_verifying(9)Begin the data verification phase.✨
start_writing(9)Begin the non-duplicate write path.✨
start_xmit(9)Transmits an skb over the ll2 interface✨
state lifetime(9)✨
state_change(9)record that the glock is now in a different state✨
state_show(9)debugfs: show overall driver and device state.✨
statfs_slow_fill(9)fill in the sg for a given RG✨
static_assert(9)check integer constant expression at build time✨
Station handling(9)✨
station table - AP Station in STA mode(9)✨
station table - Drain vs. Flush(9)✨
station table - fw restart(9)✨
station table - internal stations(9)✨
station table - introduction(9)✨
station table - locking(9)✨
stb6000_attach(9)Attach a stb6000 tuner to the supplied frontend structure.✨
stcrw_get_injected(9)Copy the artificial CRW data to CRW struct.✨
stdma_is_locked_by(9)allow lock holder to check whether it needs to release.✨
stdma_try_lock(9)attempt to acquire ST DMA interrupt "lock"✨
stfle_size(9)Actual size of the facility list as specified by stfle (number of double words)✨
sti_gdp_disable(9)✨
sti_gdp_field_cb(9)✨
sti_gdp_get_current_nodes(9)✨
sti_gdp_get_dst(9)✨
sti_gdp_get_free_nodes(9)✨
sti_hda_configure_awg(9)Configure AWG, writing instructions✨
sti_hdmi_tx3g4c28phy_start(9)Start hdmi phy macro cell tx3g4c28✨
sti_hdmi_tx3g4c28phy_stop(9)Stop hdmi phy macro cell tx3g4c28✨
sti_hqvdp_check_hw_scaling(9)✨
sti_hqvdp_disable(9)✨
sti_hqvdp_get_curr_cmd(9)✨
sti_hqvdp_get_free_cmd(9)✨
sti_hqvdp_get_next_cmd(9)✨
sti_hqvdp_start_xp70(9)✨
sti_hqvdp_update_hvsrc(9)✨
sti_hqvdp_vtg_cb(9)✨
sti_vtg_get_line_number(9)✨
sti_vtg_get_pixel_number(9)✨
stm32_adc_conf_scan_seq(9)Build regular channels scan sequence✨
stm32_adc_conv_irq_disable(9)Disable end of conversion interrupt✨
stm32_adc_conv_irq_enable(9)Enable end of conversion interrupt✨
stm32_adc_debugfs_reg_access(9)read or write register value✨
stm32_adc_get_trig_extsel(9)Get external trigger selection✨
stm32_adc_set_trig(9)Set a regular trigger✨
stm32_adc_single_conv(9)Performs a single conversion✨
stm32_adc_validate_trigger(9)validate trigger for stm32 adc✨
stm32_bsec_optee_ta_close(9)release the STM32 BSEC TA✨
stm32_bsec_optee_ta_open(9)initialize the STM32 BSEC TA✨
stm32_bsec_optee_ta_read(9)nvmem read access using TA client driver✨
stm32_bsec_optee_ta_write(9)nvmem write access using TA client driver✨
stm32_dfsdm_get_buff_cb(9)register a callback that will be called when DMA transfer period is achieved.✨
stm32_dfsdm_release_buff_cb(9)unregister buffer callback✨
stm32_dfsdm_start_dfsdm(9)start global dfsdm interface.✨
stm32_dfsdm_stop_dfsdm(9)stop global DFSDM interface.✨
stm32_dma_is_current_sg(9)check that expected sg_req is currently transferred✨
stm32_firewall_controller_register(9)Register a firewall controller to the STM32 firewall framework✨
stm32_firewall_controller_unregister(9)Unregister a firewall controller from the STM32 firewall framework✨
stm32_firewall_get_firewall(9)Get the firewall(s) associated to given device. The firewall controller reference is always the first argument of each of the access-controller property entries. The firewall ID is always the…✨
stm32_firewall_get_grant_all_access(9)Allocate and get all the firewall(s) associated to given device. Then, try to grant access rights for each element. This function is basically a helper function that wraps both…✨
stm32_firewall_grant_access(9)Request firewall access rights and grant access.✨
stm32_firewall_grant_access_by_id(9)Request firewall access rights of a given device based on a specific firewall ID✨
stm32_firewall_populate_bus(9)Populate device tree nodes that have a correct firewall configuration. This is used at boot-time only, as a sanity check between device tree and firewalls hardware configurations to prevent a…✨
stm32_firewall_release_access(9)Release access granted from a call to stm32_firewall_grant_access().✨
stm32_firewall_release_access_by_id(9)Release access granted from a call to stm32_firewall_grant_access_by_id().✨
stm32_hash_set_nblw(9)set the number of valid bytes in the last word.✨
stm32_hash_wait_busy(9)wait until hash processor is available. It return an error if the hash core is processing a block of data for more than 10 ms.✨
stm32_hash_write_ctrl(9)Initialize the hash processor, only if HASH_FLAGS_INIT is set.✨
stm32_pctl_probe(9)Common probe for stm32 pinctrl drivers.✨
STM32_PERIPHERAL_FIREWALL(9)This type of firewall protects peripherals STM32_MEMORY_FIREWALL: This type of firewall protects memories/subsets of memory zones STM32_NOTYPE_FIREWALL: Undefined firewall type✨
stm32_pinctrl_resume(9)Common resume for stm32 pinctrl drivers.✨
stm32_pinctrl_suspend(9)Common suspend for stm32 pinctrl drivers.✨
stm32_spi_can_dma(9)Determine if the transfer is eligible for DMA use✨
stm32_spi_can_poll(9)detect if poll based transfer is appropriate✨
stm32_spi_communication_type(9)return transfer communication type✨
stm32_spi_dma_config(9)configure dma slave channel depending on current transfer bits_per_word.✨
stm32_spi_dma_rx_cb(9)dma callback✨
stm32_spi_enable(9)Enable SPI controller✨
stm32_spi_prepare_mbr(9)Determine baud rate divisor value✨
stm32_spi_prepare_msg(9)set up the controller to transfer a single message✨
stm32_spi_prepare_rx_dma_mdma_chaining(9)Prepare RX DMA and MDMA chaining✨
stm32_spi_set_mbr(9)Configure baud rate divisor in host mode✨
stm32_spi_transfer_one(9)transfer a single spi_transfer✨
stm32_spi_transfer_one_dma(9)transfer a single spi_transfer using DMA✨
stm32_spi_transfer_one_setup(9)common setup to transfer a single spi_transfer either using DMA or interrupts.✨
stm32_spi_unprepare_msg(9)relax the hardware✨
stm32_timer_of_bits_get(9)get accessor helper✨
stm32_timer_of_bits_set(9)set accessor helper✨
stm32_timer_set_prescaler(9)Compute and set the prescaler register✨
stm32_timer_set_width(9)Sort out the timer width (32/16)✨
stm32_timer_start(9)Start the counter without event✨
stm32_timers_dma_burst_read(9)Read from timers registers using DMA.✨
stm32f4_adc_clk_sel(9)Select stm32f4 ADC common clock prescaler✨
stm32f4_adc_start_conv(9)Start conversions for regular channels.✨
stm32f4_i2c_handle_read(9)Handle FIFO empty interrupt in case of read✨
stm32f4_i2c_handle_rx_addr(9)Handle address matched interrupt in case of controller receiver✨
stm32f4_i2c_handle_rx_done(9)Handle byte transfer finished interrupt in case of read✨
stm32f4_i2c_handle_write(9)Handle FIFO empty interrupt in case of write✨
stm32f4_i2c_hw_config(9)Prepare I2C block✨
stm32f4_i2c_isr_error(9)Interrupt routine for I2C bus error✨
stm32f4_i2c_isr_event(9)Interrupt routine for I2C bus event✨
stm32f4_i2c_write_byte(9)Write a byte in the data register✨
stm32f4_i2c_write_msg(9)Fill the data register in write mode✨
stm32f4_i2c_xfer(9)Transfer combined I2C message✨
stm32f4_i2c_xfer_msg(9)Transfer a single I2C message✨
stm32f4_spi_get_bpw_mask(9)Return bits per word mask✨
stm32f4_spi_read_rx(9)Read bytes from Receive Data Register✨
stm32f4_spi_set_bpw(9)Configure bits per word✨
stm32f4_spi_write_tx(9)Write bytes to Transmit Data Register✨
stm32f7_spi_get_bpw_mask(9)Return bits per word mask✨
stm32f7_spi_read_rx(9)Read bytes from Receive Data Register✨
stm32f7_spi_set_bpw(9)Configure bits per word✨
stm32f7_spi_transfer_one_dma_start(9)Set SPI driver registers to start transfer using DMA✨
stm32f7_spi_write_tx(9)Write bytes to Transmit Data Register✨
stm32fx_spi_config(9)Configure SPI controller as SPI host✨
stm32fx_spi_disable(9)Disable SPI controller✨
stm32fx_spi_dma_tx_cb(9)dma callback✨
stm32fx_spi_irq_event(9)Interrupt handler for SPI controller events✨
stm32fx_spi_irq_thread(9)Thread of interrupt handler for SPI controller✨
stm32fx_spi_set_mode(9)configure communication mode✨
stm32fx_spi_transfer_one_dma_start(9)Set SPI driver registers to start transfer using DMA✨
stm32fx_spi_transfer_one_irq(9)transfer a single spi_transfer using interrupts✨
stm32h7_adc_check_selfcalib(9)Check linear calibration status✨
stm32h7_adc_prepare(9)Leave power down mode to enable ADC.✨
stm32h7_adc_read_selfcalib(9)read calibration shadow regs, save result✨
stm32h7_adc_restore_selfcalib(9)Restore saved self-calibration result✨
stm32h7_adc_selfcalib(9)Procedure to calibrate ADC✨
stm32h7_spi_config(9)Configure SPI controller✨
stm32h7_spi_data_idleness(9)configure minimum time delay inserted between two consecutive data frames in host mode✨
stm32h7_spi_disable(9)Disable SPI controller✨
stm32h7_spi_get_bpw_mask(9)Return bits per word mask✨
stm32h7_spi_get_fifo_size(9)Return fifo size✨
stm32h7_spi_irq_thread(9)Thread of interrupt handler for SPI controller✨
stm32h7_spi_number_of_data(9)configure number of data at current transfer✨
stm32h7_spi_prepare_fthlv(9)Determine FIFO threshold level✨
stm32h7_spi_read_rxfifo(9)Read bytes in Receive Data Register✨
stm32h7_spi_set_bpw(9)configure bits per word✨
stm32h7_spi_set_mode(9)configure communication mode✨
stm32h7_spi_transfer_one_dma_start(9)Set SPI driver registers to start transfer using DMA✨
stm32h7_spi_transfer_one_irq(9)transfer a single spi_transfer using interrupts✨
stm32h7_spi_transfer_one_poll(9)transfer a single spi_transfer by direct register access without interrupt usage✨
stm32h7_spi_write_txfifo(9)Write bytes in Transmit Data Register✨
stm32mp25_spi_get_bpw_mask(9)Return bits per word mask✨
stm_data_write(9)send the given payload as data packets✨
stm_find_device(9)find stm device by name✨
stm_ftrace_write(9)write data to STM via 'stm_ftrace' source✨
stm_put_device(9)drop references on the stm device✨
stm_source_link_add(9)connect an stm_source device to an stm device✨
stm_source_link_drop(9)detach stm_source from its stm device✨
stm_source_register_device(9)register an stm_source device✨
stm_source_unregister_device(9)unregister an stm_source device✨
stmmac_adjust_freq(9)✨
stmmac_adjust_time(9)✨
stmmac_axi_blen_to_mask(9)convert a burst length array to reg value✨
stmmac_axi_setup(9)parse DT parameters for programming the AXI register✨
stmmac_change_mtu(9)entry point to change MTU size for the device.✨
stmmac_check_ether_addr(9)check if the MAC addr is valid✨
stmmac_check_pcs_mode(9)verify if RGMII/SGMII is supported✨
stmmac_clear_descriptors(9)clear descriptors✨
stmmac_clear_rx_descriptors(9)clear RX descriptors✨
stmmac_clear_tx_descriptors(9)clear tx descriptors✨
stmmac_clk_csr_set(9)dynamically set the MDC clock✨
stmmac_configure_cbs(9)Configure CBS in TX queue✨
stmmac_disable_all_queues(9)Disable all queues✨
stmmac_dma_interrupt(9)DMA ISR✨
stmmac_dma_operation_mode(9)HW DMA operation mode✨
stmmac_dvr_probe(9)✨
stmmac_dvr_remove(9)✨
stmmac_eee_ctrl_timer(9)EEE TX SW timer.✨
stmmac_enable_all_queues(9)Enable all queues✨
stmmac_free_rx_buffer(9)free RX dma buffers✨
stmmac_free_tx_buffer(9)free RX dma buffers✨
stmmac_free_tx_skbufs(9)free TX skb buffers✨
stmmac_get_hw_features(9)get MAC capabilities from the HW cap. register.✨
stmmac_get_syncdevicetime(9)✨
stmmac_get_time(9)✨
stmmac_has_ip_ethertype(9)Check if packet has IP ethertype✨
stmmac_hw_init(9)Init the MAC device✨
stmmac_hw_setup(9)setup mac in a usable state.✨
stmmac_hwtstamp_get(9)read hardware timestamping.✨
stmmac_hwtstamp_set(9)control hardware timestamping.✨
stmmac_init_coalesce(9)init mitigation options.✨
stmmac_init_dma_engine(9)DMA init.✨
stmmac_init_phy(9)PHY initialization✨
stmmac_init_rx_buffers(9)init the RX descriptor buffer.✨
stmmac_init_timestamping(9)initialise timestamping✨
stmmac_init_tstamp_counter(9)init hardware timestamping counter✨
stmmac_interrupt(9)main ISR✨
stmmac_ioctl(9)Entry point for the Ioctl✨
stmmac_mac_config_rx_queues_prio(9)Configure RX Queue priority✨
stmmac_mac_config_rx_queues_routing(9)Configure RX Queue Routing✨
stmmac_mac_config_tx_queues_prio(9)Configure TX Queue priority✨
stmmac_mac_enable_rx_queues(9)Enable MAC rx queues✨
stmmac_mac_flow_ctrl(9)Configure flow control in all queues✨
stmmac_mdio_format_addr(9)format the address register✨
stmmac_mdio_read_c22(9)✨
stmmac_mdio_read_c45(9)✨
stmmac_mdio_register(9)✨
stmmac_mdio_reset(9)✨
stmmac_mdio_setup(9)Populate platform related MDIO structures.✨