STRUCT CLK_MUX(9)

📦 version 7.3.1, in nixpkgs unstable

💅 struct clk_mux(9) — the Kernel API Manual, bestie edition

okay so real talk: this one's a page from the Kernel API Manual and it's all about struct clk_mux, aka the multiplexer clock. it's giving "choose your fighter" energy and honestly? iconic.

✨ NAME ✨

struct clk_mux — the multiplexer clock, periodt 💅

🎀 SYNOPSIS 🎀

like, here's the whole vibe, verbatim, no notes:

struct clk_mux {
    struct clk_hw   hw;
    void __iomem    *reg;
    const u32       *table;
    u32 mask;
    u8 shift;
    u8 flags;
    spinlock_t *lock;
 };

🦋 Members 🦋

okay let's meet the cast, main character energy only:

  • hw — the handle between the common interfaces and the hardware-specific ones. it's the little liaison, the go-between, the group-chat admin 🫶
  • reg — the register that controls the multiplexer. this is where the actual business happens.
  • table — an array of register values that correspond to the parent index. lowkey the mapping table of your dreams.
  • mask — the mask of the multiplexer bit field. keeps things contained, as it should.
  • shift — the shift to the multiplexer bit field. gotta slide into position 💅
  • flags — hardware-specific flags. yes there are a bunch, hold on, we're getting there.
  • lock — the register lock. nobody touches the register without it, fr fr.

🌸 Description 🌸

so it's a clock with multiple selectable parents — you get options, you get range, you get choices 😌. it implements .get_parent, .set_parent and .recalc_rate.

now, the flags. buckle up bestie, there are six 💀:

  • CLK_MUX_INDEX_ONE — the register index starts at 1, not 0. yes, really. it's one-indexed, don't come for me.
  • CLK_MUX_INDEX_BIT — the register index is a single bit (a power of two).
  • CLK_MUX_HIWORD_MASK — the mux settings live only in the lower 16-bit of this register, and the mask of the mux bits lives in the higher 16-bit of this register. while you're setting the mux bits, the higher 16-bit should also be updated to indicate the changing mux bits. the way that this one has layers 🧚
  • CLK_MUX_READ_ONLY — the mux registers can't be written, only read, in the .get_parent clk_op. look but don't touch, respectfully 🙈
  • CLK_MUX_ROUND_CLOSEST — use the parent rate that is closest to the desired frequency. bestie-matchmaker behaviour, love that for us.
  • CLK_MUX_BIG_ENDIAN — by default, little endian register accesses are used for the mux register. setting this flag makes the register accesses big endian. flipping the whole byte order, no cap.
⚠️ real one: little endian is the default for the mux register accesses. CLK_MUX_BIG_ENDIAN is how you opt out of that. don't get it twisted 💖

🔥 SEE ALSO 🔥

the whole friend group, all present and accounted for, gather round:

that's the whole page, bestie, you ate it up 💖✨

✿ sourced from ./include/linux, dated October 2026, page struct clk_mux(9) — mwah, see u in the next manpage 🎀

📦 where this page comes from