STRUCT CLK_DIVIDER(9)

📦 version 7.3.1, in nixpkgs unstable

okay so bestie, welcome to the struct clk_divider(9) page from the Kernel API Manual — it’s giving adjustable divider clock and we’re gonna read it together 💅✨

✨ NAME ✨

struct clk_divider — adjustable divider clock 🕰️

📜 SYNOPSIS 📜

       struct clk_divider {
           struct clk_hw   hw;
           void __iomem    *reg;
           u8 shift;
           u8 width;
           u16 flags;
           const struct clk_div_table      *table;
           spinlock_t *lock;
        };

🧩 Members 🧩

  • hw — handle between common and hardware-specific interfaces ✨
  • reg — register containing the divider 📍
  • shift — shift to the divider bit field ⬅️
  • width — width of the divider bit field 📏
  • flags — the flag vibes go like this 👇
    • CLK_DIVIDER_ONE_BASED — by default the divisor is the value read from the register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is the raw value read from the register, with the value of zero considered invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 💅
    • CLK_DIVIDER_POWER_OF_TWO — clock divisor is 2 raised to the value read from the hardware register 🔥
    • CLK_DIVIDER_ALLOW_ZERO — Allow zero divisors. For dividers which have CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. Some hardware implementations gracefully handle this case and allow a zero divisor by not modifying their input clock (divide by one / bypass). 🫶
    • CLK_DIVIDER_HIWORD_MASK — The divider settings are only in lower 16-bit of this register, and mask of divider bits are in higher 16-bit of this register. While setting the divider bits, higher 16-bit should also be updated to indicate changing divider bits. 🧠
    • CLK_DIVIDER_ROUND_CLOSEST — Makes the best calculated divider to be rounded to the closest integer instead of the up one. 🎯
    • CLK_DIVIDER_READ_ONLY — The divider settings are preconfigured and should not be changed by the clock framework. 🚫
    • CLK_DIVIDER_MAX_AT_ZERO — For dividers which are like CLK_DIVIDER_ONE_BASED except when the value read from the register is zero, the divisor is 2^width of the field. 💥
    • CLK_DIVIDER_BIG_ENDIAN — By default little endian register accesses are used for the divider register. Setting this flag makes the register accesses big endian. 🔄
    • CLK_DIVIDER_EVEN_INTEGERS — clock divisor is 2, 4, 6, 8, 10, etc. Formula is 2 * (value read from hardware + 1). ✌️
  • table — array of value/divider pairs, last entry should have div = 0 📚
  • lock — register lock 🔒

💖 Description 💖

Clock with an adjustable divider affecting its output frequency. Implements .recalc_rate, .set_rate and .determine_rate ✨👑

🔗 SEE ALSO 🔗

mwah 💋 this page is sourced/versioned at ./include/linux, dated October 2026, and it’s literally struct clk_divider(9) — k bye bestie, go slay those dividers 🌈👑

📦 where this page comes from