PMC.HASWELLXEON(3)

🌸 NAME: PMC.HASWELLXEON(3) 🌸

pmc.haswellxeon — measurement events for Intel Haswell Xeon family CPUs 💖

📚 LIBRARY 📚

Library Functions Manual energy: Performance Counters Library (libpmc, -lpmc).

✨ SYNOPSIS ✨

#include <pmc.h>

💅 DESCRIPTION 💅

Okay bestie, so Intel Haswell CPUs contain PMCs conforming to version 2 of the Intel performance measurement architecture. These CPUs may contain up to two classes of PMCs:

• PMC_CLASS_IAF — fixed-function counters that count only one hardware event per counter.
• PMC_CLASS_IAP — programmable counters that may be configured to count one of a defined set of hardware events.

The number of PMCs available in each class and their widths need to be determined at run time by calling pmc_cpuinfo(3). No cap, that's a runtime vibe check, not a compile-time guess.

Intel Haswell Xeon PMCs are documented in “Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C”, Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Order Number: 325462-052US, Intel Corporation, September 2014.

🧚 HASWELL FIXED FUNCTION PMCS 🧚

These PMCs and their supported events are documented in pmc.iaf(3). 💫

🔥 HASWELL PROGRAMMABLE PMCS 🔥

The programmable PMCs support the following capabilities — here's the support vibe check:

• PMC_CAP_CASCADE — No
• PMC_CAP_EDGE — Yes
• PMC_CAP_INTERRUPT — Yes
• PMC_CAP_INVERT — Yes
• PMC_CAP_READ — Yes
• PMC_CAP_PRECISE — No
• PMC_CAP_SYSTEM — Yes
• PMC_CAP_TAGGING — No
• PMC_CAP_THRESHOLD — Yes
• PMC_CAP_USER — Yes
• PMC_CAP_WRITE — Yes

🎀 Event Qualifiers 🎀

Event specifiers for these PMCs support the following common qualifiers. It's giving "customize your counter." 💅

• rsp=value — configure the Off-core Response bits. The values are:
  • DMND_DATA_RD — counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches.
  • REQ_DMND_RFO — counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches.
  • REQ_DMND_IFETCH — counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches.
  • REQ_WB — counts the number of writeback (modified to exclusive) transactions.
  • REQ_PF_DATA_RD — counts the number of data cacheline reads generated by L2 prefetchers.
  • REQ_PF_RFO — counts the number of RFO requests generated by L2 prefetchers.
  • REQ_PF_IFETCH — counts the number of code reads generated by L2 prefetchers.
  • REQ_PF_LLC_DATA_RD — L2 prefetcher to L3 for loads.
  • REQ_PF_LLC_RFO — RFO requests generated by L2 prefetcher
  • REQ_PF_LLC_IFETCH — L2 prefetcher to L3 for instruction fetches.
  • REQ_BUS_LOCKS — bus lock and split lock requests.
  • REQ_STRM_ST — streaming store requests.
  • REQ_OTHER — any other request that crosses IDI, including I/O.
  • RES_ANY — catch all value for any response types.
  • RES_SUPPLIER_NO_SUPP — no Supplier Information available.
  • RES_SUPPLIER_LLC_HITM — M-state initial lookup stat in L3.
  • RES_SUPPLIER_LLC_HITE — E-state.
  • RES_SUPPLIER_LLC_HITS — S-state.
  • RES_SUPPLIER_LLC_HITF — F-state.
  • RES_SUPPLIER_LOCAL — local DRAM Controller.
  • RES_SNOOP_SNP_NONE — no details on snoop-related information.
  • RES_SNOOP_SNP_NO_NEEDED — no snoop was needed to satisfy the request.
  • RES_SNOOP_SNP_MISS — a snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores; -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM.
  • RES_SNOOP_HIT_NO_FWD — a snoop was needed and it hits in at least one snooped cache. Hit denotes a cache-line was valid before snoop effect. This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO); -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD); -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S). In the LLC Miss case, data is returned from DRAM.
  • RES_SNOOP_HIT_FWD — a snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
  • RES_SNOOP_HITM — a snoop was needed and it HitM-ed in local or remote cache. HitM denotes a cache-line was in modified state before effect as a results of snoop. This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD); -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO); -Snoop MtoS (LLC Hit, IFetch/Data_RD).
  • RES_NON_DRAM — target was non-DRAM system address. This includes MMIO transactions.
• cmask=value — configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to value.
• edge — configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true.
• inv — invert the sense of comparison when the cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the cmask qualifier.
• os — configure the PMC to count events happening at processor privilege level 0.
• usr — configure the PMC to count events occurring at privilege levels 1, 2 or 3.

If neither of the os or usr qualifiers are specified, the default is to enable both. 🫶

⭐ Event Specifiers (Programmable PMCs) ⭐

Haswell programmable PMCs support the following events. Buckle up, bestie:

• LD_BLOCKS.STORE_FORWARD — (Event 03H, Umask 02H) Loads blocked by overlapping with store buffer that cannot be forwarded.
• MISALIGN_MEM_REF.LOADS — (Event 05H, Umask 01H) Speculative cache-line split load uops dispatched to L1D.
• MISALIGN_MEM_REF.STORES — (Event 05H, Umask 02H) Speculative cache-line split Store-address uops dispatched to L1D.
• LD_BLOCKS_PARTIAL.ADDRESS_ALIAS — (Event 07H, Umask 01H) False dependencies in MOB due to partial compare on address.
• DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK — (Event 08H, Umask 01H) Misses in all TLB levels that cause a page walk of any page size.
• DTLB_LOAD_MISSES.WALK_COMPLETED_4K — (Event 08H, Umask 02H) Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.
• DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K — (Event 08H, Umask 02H) Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.
• DTLB_LOAD_MISSES.WALK_COMPLETED — (Event 08H, Umask 0EH) Completed page walks in any TLB of any page size due to demand load misses
• DTLB_LOAD_MISSES.WALK_DURATION — (Event 08H, Umask 10H) Cycle PMH is busy with a walk.
• DTLB_LOAD_MISSES.STLB_HIT_4K — (Event 08H, Umask 20H) Load misses that missed DTLB but hit STLB (4K).
• DTLB_LOAD_MISSES.STLB_HIT_2M — (Event 08H, Umask 40H) Load misses that missed DTLB but hit STLB (2M).
• DTLB_LOAD_MISSES.STLB_HIT — (Event 08H, Umask 60H) Number of cache load STLB hits. No page walk.
• DTLB_LOAD_MISSES.PDE_CACHE_MISS — (Event 08H, Umask 80H) DTLB demand load misses with low part of linear-to- physical address translation missed
• INT_MISC.RECOVERY_CYCLES — (Event 0DH, Umask 03H) Cycles waiting to recover after Machine Clears except JEClear. Set Cmask= 1.
• UOPS_ISSUED.ANY — (Event 0EH, Umask 01H) Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1 to count stalled cycles of this core.
• UOPS_ISSUED.FLAGS_MERGE — (Event 0EH, Umask 10H) Number of flags-merge uops allocated. Such uops adds delay.
• UOPS_ISSUED.SLOW_LEA — (Event 0EH, Umask 20H) Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.
• UOPS_ISSUED.SiNGLE_MUL — (Event 0EH, Umask 40H) Number of multiply packed/scalar single precision uops allocated.
• L2_RQSTS.DEMAND_DATA_RD_MISS — (Event 24H, Umask 21H) Demand Data Read requests that missed L2, no rejects.
• L2_RQSTS.DEMAND_DATA_RD_HIT — (Event 24H, Umask 41H) Demand Data Read requests that hit L2 cache.
• L2_RQSTS.ALL_DEMAND_DATA_RD — (Event 24H, Umask E1H) Counts any demand and L1 HW prefetch data load requests to L2.
• L2_RQSTS.RFO_HIT — (Event 24H, Umask 42H) Counts the number of store RFO requests that hit the L2 cache.
• L2_RQSTS.RFO_MISS — (Event 24H, Umask 22H) Counts the number of store RFO requests that miss the L2 cache.
• L2_RQSTS.ALL_RFO — (Event 24H, Umask E2H) Counts all L2 store RFO requests.
• L2_RQSTS.CODE_RD_HIT — (Event 24H, Umask 44H) Number of instruction fetches that hit the L2 cache.
• L2_RQSTS.CODE_RD_MISS — (Event 24H, Umask 24H) Number of instruction fetches that missed the L2 cache.
• L2_RQSTS.ALL_DEMAND_MISS — (Event 24H, Umask 27H) Demand requests that miss L2 cache.
• L2_RQSTS.ALL_DEMAND_REFERENCES — (Event 24H, Umask E7H) Demand requests to L2 cache.
• L2_RQSTS.ALL_CODE_RD — (Event 24H, Umask E4H) Counts all L2 code requests.
• L2_RQSTS.L2_PF_HIT — (Event 24H, Umask 50H) Counts all L2 HW prefetcher requests that hit L2.
• L2_RQSTS.L2_PF_MISS — (Event 24H, Umask 30H) Every single L2 HW prefetcher request that missed L2. All of them. Counted. 💅
• L2_RQSTS.ALL_PF — (Event 24H, Umask F8H) Okay so this one is literally all the L2 HW prefetcher requests, no filtering. The whole squad. ✨
• L2_RQSTS.MISS — (Event 24H, Umask 3FH) All requests that missed L2. Fumbled the cache, bestie. 😭
• L2_RQSTS.REFERENCES — (Event 24H, Umask FFH) All requests to L2 cache — the full guest list, no exclusions. 🎀
• L2_DEMAND_RQSTS.WB_HIT — (Event 27H, Umask 50H) Not rejected writebacks that hit L2 cache. They made it, they're thriving. 🦋
• LONGEST_LAT_CACHE.REFERENCE — (Event 2EH, Umask 4FH) Counts requests originating from the core that reference a cache line in the last level cache. Main character cache, honestly. 👑
• LONGEST_LAT_CACHE.MISS — (Event 2EH, Umask 41H) Counts each cache miss condition for references to the last level cache. Every single one. 😬
• CPU_CLK_UNHALTED.THREAD_P — (Event 3CH, Umask 00H) Counts the number of thread cycles while the thread is not in a halt state. Heads up: the thread enters the halt state when it is running the HLT instruction. Also, the core frequency may change from time to time due to power or thermal throttling — so like, don't @ her if the numbers wobble. 🔥
• CPU_CLK_THREAD_UNHALTED.REF_XCLK — (Event 3CH, Umask 01H) Increments at the frequency of XCLK (100 MHz) when not halted. Stable queen behavior. ⭐
• L1D_PEND_MISS.PENDING — (Event 48H, Umask 01H) Increments the number of outstanding L1D misses every cycle. Important: set Cmask = 1 and Edge =1 to count occurrences, iykyk. 🫶
• DTLB_STORE_MISSES.MISS_CAUSES_A_WALK — (Event 49H, Umask 01H) Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). Yes, any size. She's flexible. 💜
• DTLB_STORE_MISSES.WALK_COMPLETED_4K — (Event 49H, Umask 02H) Completed page walks due to store misses in one or more TLB levels of 4K page structure. 🎀
• DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M — (Event 49H, Umask 04H) Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure. Bigger pages, same drama. 🦋
• DTLB_STORE_MISSES.WALK_COMPLETED — (Event 49H, Umask 0EH) Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G). The whole walk, finished, done. periodt. 💅
• DTLB_STORE_MISSES.WALK_DURATION — (Event 49H, Umask 10H) Cycles PMH is busy with this walk. PMH is booked and busy, fr fr. 😮‍💨
• DTLB_STORE_MISSES.STLB_HIT_4K — (Event 49H, Umask 20H) Store misses that missed DTLB but hit STLB (4K). Rejected by the first, saved by the second. 💖
• DTLB_STORE_MISSES.STLB_HIT_2M — (Event 49H, Umask 40H) Store misses that missed DTLB but hit STLB (2M). Same energy, bigger page. ✨
• DTLB_STORE_MISSES.STLB_HIT — (Event 49H, Umask 60H) Store operations that miss the first TLB level but hit the second and do not cause page walks. No walk, no stress. 🌸
• DTLB_STORE_MISSES.PDE_CACHE_MISS — (Event 49H, Umask 80H) DTLB store misses with low part of linear-to-physical address translation missed. The translation lowkey ghosted us. 🙈
• LOAD_HIT_PRE.SW_PF — (Event 4CH, Umask 01H) Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. Plot twist: they hit the SW prefetch's buffer. 😭
• LOAD_HIT_PRE.HW_PF — (Event 4CH, Umask 02H) Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. Same vibe, but the hardware did the prefetching. 🔥
• L1D.REPLACEMENT — (Event 51H, Umask 01H) Counts the number of lines brought into the L1 data cache. Welcome to the L1D, new lines, we've been expecting you. 👑
• MOVE_ELIMINATION.INT_NOT_ELIMINATED — (Event 58H, Umask 04H) Number of integer Move Elimination candidate uops that were not eliminated. They tried and honestly? They failed. 💀
• MOVE_ELIMINATION.SMID_NOT_ELIMINATED — (Event 58H, Umask 08H) Number of SIMD Move Elimination candidate uops that were not eliminated. Same heartbreak, SIMD edition. 😭
• MOVE_ELIMINATION.INT_ELIMINATED — (Event 58H, Umask 01H) Unhalted core cycles when the thread is in ring 0. (Yes babes, that's what the manpage says for this one — copy that exactly, no notes. 🤨)
• MOVE_ELIMINATION.SMID_ELIMINATED — (Event 58H, Umask 02H) Number of SIMD Move Elimination candidate uops that were eliminated. Slayed. ✨
• CPL_CYCLES.RING0 — (Event 5CH, Umask 02H) Unhalted core cycles when the thread is in ring 0. Privileged era. 👑
• CPL_CYCLES.RING123 — (Event 5CH, Umask 01H) Unhalted core cycles when the thread is not in ring 0. Peasant rings, but make it cute. 🎀
• RS_EVENTS.EMPTY_CYCLES — (Event 5EH, Umask 01H) Cycles the RS is empty for the thread. Nobody home. 💀
• OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD — (Event 60H, Umask 01H) Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles. 🦋
• OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD — (Event 60H, Umask 02H) Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles. Note: the manpage says "code Read" here — that's the actual text, bestie, we don't editorialize. 🙈
• OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO — (Event 60H, Umask 04H) Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles. ✨
• OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD — (Event 60H, Umask 08H) Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles. 🔥
• LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION — (Event 63H, Umask 01H) Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. Locked down, both of them. 💅
• LOCK_CYCLES.CACHE_LOCK_DURATION — (Event 63H, Umask 02H) Cycles in which the L1D is locked. Just L1D this time. 🎀
• IDQ.EMPTY — (Event 79H, Umask 02H) Counts cycles the IDQ is empty. The queue is giving empty. ⭐
• IDQ.MITE_UOPS — (Event 79H, Umask 04H) Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles. 🧚
• IDQ.DSB_UOPS — (Event 79H, Umask 08H) Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles. (That stray period is in the original, don't come for me. 😅)
• IDQ.MS_DSB_UOPS — (Event 79H, Umask 10H) Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery. 🦋
• IDQ.MS_MITE_UOPS — (Event 79H, Umask 20H) ncrement each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles. ("ncrement" — yes, the original says that. Keeping it real. 💀)
• IDQ.MS_UOPS — (Event 79H, Umask 30H) Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles. Either path, she doesn't care. 🫶
• IDQ.ALL_DSB_CYCLES_ANY_UOPS — (Event 79H, Umask 18H) Counts cycles DSB is delivered at least one uops. Set Cmask = 1. 🌸
• IDQ.ALL_DSB_CYCLES_4_UOPS — (Event 79H, Umask 18H) Counts cycles DSB is delivered four uops. Set Cmask =4. 🍓
• IDQ.ALL_MITE_CYCLES_ANY_UOPS — (Event 79H, Umask 24H) Counts cycles MITE is delivered at least one uops. Set Cmask = 1. ✨
• IDQ.ALL_MITE_CYCLES_4_UOPS — (Event 79H, Umask 24H) Counts cycles MITE is delivered four uops. Set Cmask =4. 💜
• IDQ.MITE_ALL_UOPS — (Event 79H, Umask 3CH) # of uops delivered to IDQ from any path. Any path!! inclusive queen. 🌈
• ICACHE.MISSES — (Event 80H, Umask 02H) Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses. 💅
• ITLB_MISSES.MISS_CAUSES_A_WALK — (Event 85H, Umask 01H) Misses in ITLB that causes a page walk of any page size. 🎀
• ITLB_MISSES.WALK_COMPLETED_4K — (Event 85H, Umask 02H) Completed page walks due to misses in ITLB 4K page entries. 🦋
• TLB_MISSES.WALK_COMPLETED_2M_4M — (Event 85H, Umask 04H) Completed page walks due to misses in ITLB 2M/4M page entries. (Yes, the name here is TLB_MISSES.WALK_COMPLETED_2M_4M and not ITLB_MISSES... — that's literally what the page says, don't blame me bestie 🙈)
• ITLB_MISSES.WALK_COMPLETED — (Event 85H, Umask 0EH) Completed page walks in ITLB of any page size. 👑
• ITLB_MISSES.WALK_DURATION — (Event 85H, Umask 10H) Cycle PMH is busy with a walk. PMH is once again booked and busy. 😮‍💨
• ITLB_MISSES.STLB_HIT_4K — (Event 85H, Umask 20H) ITLB misses that hit STLB (4K). 💖
• ITLB_MISSES.STLB_HIT_2M — (Event 85H, Umask 40H) ITLB misses that hit STLB (2K). And yes, the original really does say (2K) here while every other entry says 2M — we are faithfully reproducing the text, no cap. 😭
• ITLB_MISSES.STLB_HIT — (Event 85H, Umask 60H) TLB misses that hit STLB. No page walk. No walk, no problem. 🌸
• ILD_STALL.LCP — (Event 87H, Umask 01H) Stalls caused by changing prefix length of the instruction. The prefix changed its whole vibe and everyone stalled. 💀
• ILD_STALL.IQ_FULL — (Event 87H, Umask 04H) Stall cycles due to IQ is full. Too many people in the IQ, nobody can move. 🍓
• BR_INST_EXEC.NONTAKEN_COND — (Event 88H, Umask 41H) Count conditional near branch instructions that were executed (but not necessarily retired) and not taken. She looked at the branch and said "no <3". 🙈
• BR_INST_EXEC.TAKEN_COND — (Event 88H, Umask 81H) Count conditional near branch instructions that were executed (but not necessarily retired) and taken. She said "yes <3". 💖
• BR_INST_EXEC.DIRECT_JMP — (Event 88H, Umask 82H) Count all unconditional near branch instructions excluding calls and indirect branches. Direct, no drama. ✨
• BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET — (Event 88H, Umask 84H) Count executed indirect near branch instructions that are not calls nor returns. Not a call, not a return, just vibes. 🦋
• BR_INST_EXEC.RETURN_NEAR — (Event 88H, Umask 88H) Count indirect near branches that have a return mnemonic. She's coming back home. 💜
• BR_INST_EXEC.DIRECT_NEAR_CALL — (Event 88H, Umask 90H) Count unconditional near call branch instructions, excluding non call branch, executed. 🎀
• BR_INST_EXEC.INDIRECT_NEAR_CALL — (Event 88H, Umask A0H) Count indirect near calls, including both register and memory indirect, executed. Register and memory indirect — she contains multitudes. 👑
• BR_INST_EXEC.ALL_BRANCHES — (Event 88H, Umask FFH) Counts all near executed branches (not necessarily retired). The entire cast. 🌈
• BR_MISP_EXEC.NONTAKEN_COND — (Event 89H, Umask 41H) Count conditional near branch instructions mispredicted as nontaken. Wrong guess, bestie. 💀
• BR_MISP_EXEC.TAKEN_COND — (Event 89H, Umask 81H) Count conditional near branch instructions mispredicted as taken. Also the wrong guess, opposite direction. 😭
• BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET — (Event 89H, Umask 84H) Count mispredicted indirect near branch instructions that are not calls nor returns. 🦋
• BR_MISP_EXEC.RETURN_NEAR — (Event 89H, Umask 88H) Count mispredicted indirect near branches that have a return mnemonic. She came back and the predictor was NOT ready. 🙈
• BR_MISP_EXEC.DIRECT_NEAR_CALL — (Event 89H, Umask 90H) Count mispredicted unconditional near call branch instructions, excluding non call branch, executed. 🎀
• BR_MISP_EXEC.INDIRECT_NEAR_CALL — (Event 89H, Umask A0H) Count mispredicted indirect near calls, including both register and memory indirect, executed. ✨
• BR_MISP_EXEC.ALL_BRANCHES — (Event 89H, Umask FFH) Counts all mispredicted near executed branches (not necessarily retired). Every flop, all at once. 💅
• IDQ_UOPS_NOT_DELIVERED.CORE — (Event 9CH, Umask 01H) Count number of non-delivered uops to RAT per thread. The uops that never showed up to the party. 😭
• UOPS_EXECUTED_PORT.PORT_0 — (Event A1H, Umask 01H) Cycles which a Uop is dispatched on port 0 in this thread. Port 0 is carrying. 🔥
• UOPS_EXECUTED_PORT.PORT_1 — (Event A1H, Umask 02H) Cycles which a Uop is dispatched on port 1 in this thread. Port 1 said "my turn". ⭐
• UOPS_EXECUTED_PORT.PORT_2 — (Event A1H, Umask 04H) counts the cycles where a uop gets dispatched on port 2, in this thread specifically.
• UOPS_EXECUTED_PORT.PORT_3 — (Event A1H, Umask 08H) same deal but port 3, this thread. 💅
• UOPS_EXECUTED_PORT.PORT_4 — (Event A1H, Umask 10H) cycles a uop is dispatched on port 4, this thread.
• UOPS_EXECUTED_PORT.PORT_5 — (Event A1H, Umask 20H) cycles a uop is dispatched on port 5, this thread.
• UOPS_EXECUTED_PORT.PORT_6 — (Event A1H, Umask 40H) cycles a uop is dispatched on port 6, this thread.
• UOPS_EXECUTED_PORT.PORT_7 — (Event A1H, Umask 80H) cycles a uop is dispatched on port 7, this thread. that's the whole port fam, we love a complete set ✨
• RESOURCE_STALLS.ANY — (Event A2H, Umask 01H) cycles where allocation is stalled for resource-related reasons.
• RESOURCE_STALLS.RS — (Event A2H, Umask 04H) cycles stalled because there's no eligible RS entry available.
• RESOURCE_STALLS.SB — (Event A2H, Umask 08H) cycles stalled because no store buffers are available — and heads up, that's not counting draining from sync. 🫶
• RESOURCE_STALLS.ROB — (Event A2H, Umask 10H) cycles stalled because the re-order buffer is full. classic.
• CYCLE_ACTIVITY.CYCLES_L2_PENDING — (Event A3H, Umask 01H) cycles with pending L2 miss loads. set Cmask=2 to count the cycle.
• CYCLE_ACTIVITY.CYCLES_LDM_PENDING — (Event A3H, Umask 02H) cycles with pending memory loads. set Cmask=2 to count the cycle.
• CYCLE_ACTIVITY.STALLS_L2_PENDING — (Event A3H, Umask 05H) the number of loads that missed L2.
• CYCLE_ACTIVITY.CYCLES_L1D_PENDING — (Event A3H, Umask 08H) cycles with pending L1 cache miss loads. set Cmask=8 to count the cycle. yes the cmask is different from the others, read it again bestie 👀

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• ITLB.ITLB_FLUSH — (Event AEH, Umask 01H) counts how many ITLB flushes happen — and it includes the 4k/2M/4M pages.
• OFFCORE_REQUESTS.DEMAND_DATA_RD — (Event B0H, Umask 01H) demand data read requests that got sent to the uncore.
• OFFCORE_REQUESTS.DEMAND_CODE_RD — (Event B0H, Umask 02H) demand code read requests sent to the uncore.
• OFFCORE_REQUESTS.DEMAND_RFO — (Event B0H, Umask 04H) demand RFO read requests sent to the uncore — this one includes regular RFOs, locks, and ItoM.
• OFFCORE_REQUESTS.ALL_DATA_RD — (Event B0H, Umask 08H) data read requests sent to the uncore, demand and prefetch both. 🦋
• UOPS_EXECUTED.CORE — (Event B1H, Umask 02H) counts the total number of uops to be executed per-core, each cycle.
• OFF_CORE_RESPONSE_0 — (Event B7H, Umask 01H) this one requires MSR 01A6H.
• OFF_CORE_RESPONSE_1 — (Event BBH, Umask 01H) this one requires MSR 01A7H. not the same MSR, don't mix 'em up 💀
• PAGE_WALKER_LOADS.DTLB_L1 — (Event BCH, Umask 11H) number of DTLB page walker loads that hit in the L1+FB.
• PAGE_WALKER_LOADS.ITLB_L1 — (Event BCH, Umask 21H) number of ITLB page walker loads that hit in the L1+FB.
• PAGE_WALKER_LOADS.DTLB_L2 — (Event BCH, Umask 12H) DTLB page walker loads that hit in the L2.
• PAGE_WALKER_LOADS.ITLB_L2 — (Event BCH, Umask 22H) ITLB page walker loads that hit in the L2.
• PAGE_WALKER_LOADS.DTLB_L3 — (Event BCH, Umask 14H) DTLB page walker loads that hit in the L3.
• PAGE_WALKER_LOADS.ITLB_L3 — (Event BCH, Umask 24H) ITLB page walker loads that hit in the L3.
• PAGE_WALKER_LOADS.DTLB_MEMORY — (Event BCH, Umask 18H) number of DTLB page walker loads coming from memory.
• PAGE_WALKER_LOADS.ITLB_MEMORY — (Event BCH, Umask 28H) number of ITLB page walker loads coming from memory. the BCH saga is complete, we ate 🌈
• TLB_FLUSH.DTLB_THREAD — (Event BDH, Umask 01H) DTLB flush attempts on the thread-specific entries.
• TLB_FLUSH.STLB_ANY — (Event BDH, Umask 20H) counts the number of STLB flush attempts.

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• INST_RETIRED.ANY_P — (Event C0H, Umask 00H) number of instructions at retirement.
• INST_RETIRED.ALL — (Event C0H, Umask 01H) the precise instruction retired event, with hardware doing its thing to reduce the effect of PEBS shadow in IP distribution.
• OTHER_ASSISTS.AVX_TO_SSE — (Event C1H, Umask 08H) number of transitions from AVX-256 to legacy SSE when a penalty applies.
• OTHER_ASSISTS.SSE_TO_AVX — (Event C1H, Umask 10H) number of transitions from SSE to AVX-256 when a penalty applies. the other direction, iconic 🎀
• OTHER_ASSISTS.ANY_WB_ASSIST — (Event C1H, Umask 40H) number of microcode assists invoked by hardware upon uop writeback.
• UOPS_RETIRED.ALL — (Event C2H, Umask 01H) counts the number of micro-ops retired. pro tip: use cmask=1 and invert to count active cycles or stalled cycles instead.
• UOPS_RETIRED.RETIRE_SLOTS — (Event C2H, Umask 02H) counts the number of retirement slots used each cycle.
• MACHINE_CLEARS.MEMORY_ORDERING — (Event C3H, Umask 02H) counts machine clears caused by memory order conflicts.
• MACHINE_CLEARS.SMC — (Event C3H, Umask 04H) number of self-modifying-code machine clears detected.
• MACHINE_CLEARS.MASKMOV — (Event C3H, Umask 20H) counts executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. 😭

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• BR_INST_RETIRED.ALL_BRANCHES — (Event C4H, Umask 00H) branch instructions at retirement.
• BR_INST_RETIRED.CONDITIONAL — (Event C4H, Umask 01H) counts the number of conditional branch instructions. supports PEBS retired.
• BR_INST_RETIRED.NEAR_CALL — (Event C4H, Umask 02H) direct and indirect near call instructions retired.
• BR_INST_RETIRED.ALL_BRANCHES — (Event C4H, Umask 04H) counts the number of branch instructions retired. yes queen the name appears twice in this list with different umasks — that's genuinely how the source has it, i'm not touching it 🙈
• BR_INST_RETIRED.NEAR_RETURN — (Event C4H, Umask 08H) counts the number of near return instructions retired.
• BR_INST_RETIRED.NOT_TAKEN — (Event C4H, Umask 10H) counts the number of not-taken branch instructions retired.
• BR_INST_RETIRED.NEAR_TAKEN — (Event C4H, Umask 20H) number of near taken branches retired. (heads up: in the raw source this line is a little mangled — there's stray text welded onto the front of it — but the event, the C4H, the Umask 20H and the meaning are all exactly this 💜)
• BR_INST_RETIRED.FAR_BRANCH — (Event C4H, Umask 40H) number of far branches retired.
• BR_MISP_RETIRED.ALL_BRANCHES — (Event C5H, Umask 00H) mispredicted branch instructions at retirement.
• BR_MISP_RETIRED.CONDITIONAL — (Event C5H, Umask 01H) mispredicted conditional branch instructions retired.
• BR_MISP_RETIRED.CONDITIONAL — (Event C5H, Umask 04H) mispredicted macro branch instructions retired. and there's the second double-name of the page, same deal — the label in the source is CONDITIONAL, the umask is 04H, the description is macro branches. no cap. 💅

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• FP_ASSIST.X87_OUTPUT — (Event CAH, Umask 02H) number of X87 FP assists caused by output values.
• FP_ASSIST.X87_INPUT — (Event CAH, Umask 04H) number of X87 FP assists caused by input values.
• FP_ASSIST.SIMD_OUTPUT — (Event CAH, Umask 08H) number of SIMD FP assists caused by output values.
• FP_ASSIST.SIMD_INPUT — (Event CAH, Umask 10H) number of SIMD FP assists caused by input values.
• FP_ASSIST.ANY — (Event CAH, Umask 1EH) cycles with any input/output SSE* or FP assists.
• ROB_MISC_EVENTS.LBR_INSERTS — (Event CCH, Umask 20H) counts the cases where hardware saves new LBR records.
• MEM_TRANS_RETIRED.LOAD_LATENCY — (Event CDH, Umask 01H) randomly sampled loads whose latency goes above a user-defined threshold. quick heads up: only a small fraction of the overall loads get sampled, because, well… randomization. 🎲

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• MEM_UOPS_RETIRED.STLB_MISS_LOADS — (Event D0H, Umask 11H) counts retired load uops that missed the STLB.
• MEM_UOPS_RETIRED.STLB_MISS_STORES — (Event D0H, Umask 12H) counts retired store uops that missed the STLB.
• MEM_UOPS_RETIRED.SPLIT_LOADS — (Event D0H, Umask 41H) counts retired load uops that got split across a cache line.
• MEM_UOPS_RETIRED.SPLIT_STORES — (Event D0H, Umask 42H) counts retired store uops that got split across a cache line.
• MEM_UOPS_RETIRED.ALL_LOADS — (Event D0H, Umask 81H) counts all retired load uops. all of them. every single one. 👑
• MEM_UOPS_RETIRED.ALL_STORES — (Event D0H, Umask 82H) counts all retired store uops.
• MEM_LOAD_UOPS_RETIRED.L1_HIT — (Event D1H, Umask 01H) retired load uops whose data sources were L1 cache hits.
• MEM_LOAD_UOPS_RETIRED.L2_HIT — (Event D1H, Umask 02H) retired load uops whose data sources were L2 cache hits.
• MEM_LOAD_UOPS_RETIRED.LLC_HIT — (Event D1H, Umask 04H) retired load uops whose data sources were LLC cache hits.
• MEM_LOAD_UOPS_RETIRED.L2_MISS — (Event D1H, Umask 10H) retired load uops that missed L2. anything with an unknown data source is excluded, fyi.
• MEM_LOAD_UOPS_RETIRED.HIT_LFB — (Event D1H, Umask 40H) retired load uops whose data sources were load uops that missed L1 but hit the FB — that's because of a preceding miss to the same cache line, with the data not ready. yeah, it's a whole situation 😭
• MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS — (Event D2H, Umask 01H) retired load uops whose data sources were an LLC hit with a cross-core snoop that missed in the on-pkg core cache.
• MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT — (Event D2H, Umask 02H) retired load uops whose data sources were LLC and cross-core snoop hits in the on-pkg core cache.
• MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM — (Event D2H, Umask 04H) retired load uops whose data sources were HitM responses from shared LLC.
• MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE — (Event D2H, Umask 08H) retired load uops whose data sources were hits in the LLC with no snoops required. the chill one of the group 🌸
• MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM — (Event D3H, Umask 01H) retired load uops whose data sources missed the LLC but got serviced from local dram.
• BACLEARS.ANY — (Event E6H, Umask 1FH) number of front end re-steers caused by a BPU misprediction.

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• L2_TRANS.DEMAND_DATA_RD — (Event F0H, Umask 01H) demand data read requests that access the L2 cache.
• L2_TRANS.RFO — (Event F0H, Umask 02H) RFO requests that access the L2 cache.
• L2_TRANS.CODE_RD — (Event F0H, Umask 04H) L2 cache accesses that happen while fetching instructions.
• L2_TRANS.ALL_PF — (Event F0H, Umask 08H) any MLC or LLC hardware prefetch that accesses L2 — rejects included.
• L2_TRANS.L1D_WB — (Event F0H, Umask 10H) L1D writebacks that access the L2 cache.
• L2_TRANS.L2_FILL — (Event F0H, Umask 20H) L2 fill requests that access the L2 cache.
• L2_TRANS.L2_WB — (Event F0H, Umask 40H) L2 writebacks that access the L2 cache. and that's the F0H fam, all seven of them, slay 💖
• L2_TRANS.ALL_REQUESTS — (Event F0H, Umask 80H) transactions that are out here accessing the L2 pipe. 💅
• L2_LINES_IN.I — (Event F1H, Umask 01H) L2 cache lines in I state that are filling up L2.
• L2_LINES_IN.S — (Event F1H, Umask 02H) L2 cache lines in S state filling L2.
• L2_LINES_IN.E — (Event F1H, Umask 04H) L2 cache lines in E state filling L2.
• L2_LINES_IN.ALL — (Event F1H, Umask 07H) L2 cache lines filling L2, periodt — the whole vibe check in one counter. ✨
• L2_LINES_OUT.DEMAND_CLEAN — (Event F2H, Umask 05H) clean L2 cache lines getting evicted by demand. they had a good run 🫶
• L2_LINES_OUT.DEMAND_DIRTY — (Event F2H, Umask 06H) dirty L2 cache lines evicted by demand. messy, but make it cache 💀

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🌈 SEE ALSO 🌈

okay bestie, here's the whole friend group — go read these next, fr fr:

• pmc(3)
• pmc.amd(3)
• pmc.atom(3)
• pmc.core(3)
• pmc.corei7(3)
• pmc.corei7uc(3)
• pmc.haswell(3)
• pmc.haswelluc(3)
• pmc.iaf(3)
• pmc.ivybridge(3)
• pmc.ivybridgexeon(3)
• pmc.sandybridge(3)
• pmc.sandybridgeuc(3)
• pmc.sandybridgexeon(3)
• pmc.soft(3)
• pmc.tsc(3)
• pmc.ucf(3)
• pmc.westmere(3)
• pmc.westmereuc(3)
• pmc_cpuinfo(3)
• pmclog(3)
• hwpmc(4)

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🎀 HISTORY 🎀

Support for the Haswell Xeon microarchitecture first showed up in FreeBSD 10.2. it's been iconic since day one, no cap. ⭐

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👑 AUTHORS 👑

The Performance Counters Library (libpmc, -lpmc) library was written by Joseph Koshy ⟨jkoshy@FreeBSD.org⟩. The support for the Haswell Xeon microarchitecture was written by Randall Stewart ⟨rrs@FreeBSD.org⟩.

like… literally thank you both for your service 🫡💖

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and that's the whole page, bestie! go count some cache lines, slay, and remember: every single one of those events is right there waiting for you. periodt. 🦋🌸

Debian · November 21, 2014 · PMC.HASWELLXEON(3) — mwah, that's a wrap 💅✨