PMC.COREI7(3)

📦
version 15.1 · 2 versions
, in freebsd 15.1

🌸 PMC.COREI7(3) 🌸

okay so bestie, you found the manual page for pmc.corei7 and honestly? it's giving "deep lore" energy. this is the page where libpmc spills the tea on how to measure stuff on Intel Core i7 and Xeon 5500 family CPUs. it's a long one so hydrate first 💖

✨ NAME ✨

pmc.corei7 — measurement events for Intel Core i7 and Xeon 5500 family CPUs 🎀

📚 LIBRARY 📚

Performance Counters Library (libpmc, -lpmc)

🧚 SYNOPSIS 🧚

#include <pmc.h>

that's it. one include. iconic behavior, no notes 💅

💫 DESCRIPTION 💫

so. Intel Core i7 CPUs contain PMCs conforming to version 2 of the Intel performance measurement architecture. These CPUs may contain up to three classes of PMCs:

  • PMC_CLASS_IAF — fixed-function counters that count only one hardware event per counter. no customization, no choices, she already knows what she wants 🫶
  • PMC_CLASS_IAP — programmable counters, meaning you can configure them to count one of a defined set of hardware events. main character energy, you pick the vibe ✨

the number of PMCs available in each class and their widths need to be determined at run time by calling pmc_cpuinfo(3). like, don't guess, bestie — ask the CPU nicely first 🌸

Intel Core i7 and Xeon 5500 PMCs are documented in “Volume 3B: System Programming Guide, Part 2”, Intel(R) 64 and IA-32 Architectures Software Developes Manual, Order Number: 253669-033US, Intel Corporation, December 2009. (yes, the manual is old enough to have a whole past life. respect your elders 😭)

🔥 COREI7 AND XEON 5500 FIXED FUNCTION PMCS 🔥

these PMCs and their supported events are documented in pmc.iaf(3). heads up though: not all CPUs in this family implement fixed-function counters. so check before you count, no cap 💀

🦋 COREI7 AND XEON 5500 PROGRAMMABLE PMCS 🦋

the programmable PMCs support the following capabilities:

  • PMC_CAP_CASCADE — No 🙈
  • PMC_CAP_EDGE — Yes 💖
  • PMC_CAP_INTERRUPT — Yes ⚡
  • PMC_CAP_INVERT — Yes 🔄
  • PMC_CAP_READ — Yes 📖
  • PMC_CAP_PRECISE — No 😔
  • PMC_CAP_SYSTEM — Yes 👑
  • PMC_CAP_TAGGING — No 🚫
  • PMC_CAP_THRESHOLD — Yes 🎚️
  • PMC_CAP_USER — Yes 🧍
  • PMC_CAP_WRITE — Yes ✍️

🎀 Event Qualifiers 🎀

event specifiers for these PMCs support the following common qualifiers:

  • rsp=value — configure the Off-core Response bits. and here's the whole menu, bestie, it's a lot:
    • DMND_DATA_RD — counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. does not count L2 data read prefetches or instruction fetches.
    • DMND_RFO — counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. does not count L2 RFO.
    • DMND_IFETCH — counts the number of demand and DCU prefetch instruction cacheline reads. does not count L2 code read prefetches.
    • WB — counts the number of writeback (modified to exclusive) transactions.
    • PF_DATA_RD — counts the number of data cacheline reads generated by L2 prefetchers.
    • PF_RFO — counts the number of RFO requests generated by L2 prefetchers.
    • PF_IFETCH — counts the number of code reads generated by L2 prefetchers.
    • OTHER — counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock.
    • UNCORE_HIT — L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping).
    • OTHER_CORE_HIT_SNP — L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean).
    • OTHER_CORE_HITM — L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM).
    • REMOTE_CACHE_FWD — L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (remote home requests are not counted 🚫)
    • REMOTE_DRAM — L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAM.
    • LOCAL_DRAM — L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM.
    • NON_DRAM — non-DRAM requests that were serviced by IOH.
  • cmask=value — configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to value. like a little threshold gate, she's picky 🎚️
  • edge — configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. if specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. one and done, periodt ✨
  • inv — invert the sense of comparison when the cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the cmask qualifier. flip it and reverse it 🔄
  • os — configure the PMC to count events happening at processor privilege level 0. 👑
  • usr — configure the PMC to count events occurring at privilege levels 1, 2 or 3. 🧍

if neither of the os or usr qualifiers are specified, the default is to enable both. she said why choose 💅

🌈 Event Specifiers (Programmable PMCs) 🌈

Core i7 and Xeon 5500 programmable PMCs support the following events. buckle up, there are a lot of them and every single one is here 🫶

  • SB_DRAIN.ANY — (Event 04H, Umask 07H) counts the number of store buffer drains.
  • STORE_BLOCKS.AT_RET — (Event 06H, Umask 04H) counts number of loads delayed with at-Retirement block code. the following loads need to be executed at retirement and wait for all senior stores on the same thread to be drained: load splitting across 4K boundary (page split), load accessing uncacheable (UC or USWC) memory, load lock, and load with page table in UC or USWC memory region. it's giving "waiting in line behind everyone" 😭
  • STORE_BLOCKS.L1D_BLOCK — (Event 06H, Umask 08H) cacheable loads delayed with L1D block code
  • PARTIAL_ADDRESS_ALIAS — (Event 07H, Umask 01H) counts false dependency due to partial address aliasing
  • DTLB_LOAD_MISSES.ANY — (Event 08H, Umask 01H) counts all load misses that cause a page walk
  • DTLB_LOAD_MISSES.WALK_COMPLETED — (Event 08H, Umask 02H) counts number of completed page walks due to load miss in the STLB.
  • DTLB_LOAD_MISSES.STLB_HIT — (Event 08H, Umask 10H) number of cache load STLB hits
  • DTLB_LOAD_MISSES.PDE_MISS — (Event 08H, Umask 20H) number of DTLB cache load misses where the low part of the linear to physical address translation was missed.
  • DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED — (Event 08H, Umask 80H) counts number of completed large page walks due to load miss in the STLB.
  • MEM_INST_RETIRED.LOADS — (Event 0BH, Umask 01H) counts the number of instructions with an architecturally-visible store retired on the architected path. in conjunction with ld_lat facility
  • MEM_INST_RETIRED.STORES — (Event 0BH, Umask 02H) counts the number of instructions with an architecturally-visible store retired on the architected path. in conjunction with ld_lat facility
  • MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD — (Event 0BH, Umask 10H) counts the number of instructions exceeding the latency specified with ld_lat facility. in conjunction with ld_lat facility
  • MEM_STORE_RETIRED.DTLB_MISS — (Event 0CH, Umask 01H) the event counts the number of retired stores that missed the DTLB. the DTLB miss is not counted if the store operation causes a fault. does not counter prefetches. counts both primary and secondary misses to the TLB
  • UOPS_ISSUED.ANY — (Event 0EH, Umask 01H) counts the number of Uops issued by the Register Allocation Table to the Reservation Station, i.e. the UOPs issued from the front end to the back end. 🏃‍♀️
  • UOPS_ISSUED.STALLED_CYCLES — (Event 0EH, Umask 01H) counts the number of cycles no Uops issued by the Register Allocation Table to the Reservation Station, i.e. the UOPs issued from the front end to the back end. set invert=1, cmask = 1 💀
  • UOPS_ISSUED.FUSED — (Event 0EH, Umask 02H) counts the number of fused Uops that were issued from the Register Allocation Table to the Reservation Station.
  • MEM_UNCORE_RETIRED.L3_DATA_MISS_UNKNOWN — (Event 0FH, Umask 01H) counts number of memory load instructions retired where the memory reference missed L3 and data source is unknown. available only for CPUID signature 06_2EH
  • MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM — (Event 0FH, Umask 02H) counts number of memory load instructions retired where the memory reference hit modified data in a sibling core residing on the same socket.
  • MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT — (Event 0FH, Umask 08H) counts number of memory load instructions retired where the memory reference missed the L1, L2 and L3 caches and HIT in a remote socket's cache. only counts locally homed lines.
  • MEM_UNCORE_RETIRED.REMOTE_DRAM — (Event 0FH, Umask 10H) counts number of memory load instructions retired where the memory reference missed the L1, L2 and L3 caches and was remotely homed. this includes both DRAM access and HITM in a remote socket's cache for remotely homed lines.
  • MEM_UNCORE_RETIRED.LOCAL_DRAM — (Event 0FH, Umask 20H) counts number of memory load instructions retired where the memory reference missed the L1, L2 and L3 caches and required a local socket memory reference. this includes locally homed cachelines that were in a modified state in another socket.
  • MEM_UNCORE_RETIRED.UNCACHEABLE — (Event 0FH, Umask 80H) counts number of memory load instructions retired where the memory reference missed the L1, L2 and L3 caches and to perform I/O. available only for CPUID signature 06_2EH

okay that's the end of part 1 bestie, don't go anywhere, there's more coming 🌸💖

FP_COMP_OPS_EXE.X87

(Event 10H, Umask 01H) — Counts the number of FP Computational Uops Executed, bestie. And like, what counts as an FP Computational Uop? The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. 💅 One lil caveat tho: this event does not distinguish an FADD used in the middle of a transcendental flow from a separate FADD instruction.

FP_COMP_OPS_EXE.MMX

(Event 10H, Umask 02H) — Counts number of MMX Uops executed. that's it, that's the vibe ✨

FP_COMP_OPS_EXE.SSE_FP

(Event 10H, Umask 04H) — Counts number of SSE and SSE2 FP uops executed.

FP_COMP_OPS_EXE.SSE2_INTEGER

(Event 10H, Umask 08H) — Counts number of SSE2 integer uops executed.

FP_COMP_OPS_EXE.SSE_FP_PACKED

(Event 10H, Umask 10H) — Counts number of SSE FP packed uops executed.

FP_COMP_OPS_EXE.SSE_FP_SCALAR

(Event 10H, Umask 20H) — Counts number of SSE FP scalar uops executed.

FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION

(Event 10H, Umask 40H) — Counts number of SSE* FP single precision uops executed.

FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION

(Event 10H, Umask 80H) — Counts number of SSE* FP double precision uops executed.

SIMD_INT_128.PACKED_MPY

(Event 12H, Umask 01H) — Counts number of 128 bit SIMD integer multiply operations. math era 🔥

SIMD_INT_128.PACKED_SHIFT

(Event 12H, Umask 02H) — Counts number of 128 bit SIMD integer shift operations.

SIMD_INT_128.PACK

(Event 12H, Umask 04H) — Counts number of 128 bit SIMD integer pack operations.

SIMD_INT_128.UNPACK

(Event 12H, Umask 08H) — Counts number of 128 bit SIMD integer unpack operations.

SIMD_INT_128.PACKED_LOGICAL

(Event 12H, Umask 10H) — Counts number of 128 bit SIMD integer logical operations.

SIMD_INT_128.PACKED_ARITH

(Event 12H, Umask 20H) — Counts number of 128 bit SIMD integer arithmetic operations.

SIMD_INT_128.SHUFFLE_MOVE

(Event 12H, Umask 40H) — Counts number of 128 bit SIMD integer shuffle and move operations.

LOAD_DISPATCH.RS

(Event 13H, Umask 01H) — Counts number of loads dispatched from the Reservation Station that bypass the Memory Order Buffer. scootin' right past 👑

LOAD_DISPATCH.RS_DELAYED

(Event 13H, Umask 02H) — Counts the number of delayed RS dispatches at the stage latch. And like, the lore here: if an RS dispatch can not bypass to LB, it has another chance to dispatch from the one-cycle delayed staging latch before it is written into the LB. second chances, we love to see it 🫶

LOAD_DISPATCH.MOB

(Event 13H, Umask 04H) — Counts the number of loads dispatched from the Reservation Station to the Memory Order Buffer.

LOAD_DISPATCH.ANY

(Event 13H, Umask 07H) — Counts all loads dispatched from the Reservation Station. the whole squad fr fr

ARITH.CYCLES_DIV_BUSY

(Event 14H, Umask 01H) — Counts the number of cycles the divider is busy executing divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE. Set 'edge =1, invert=1, cmask=1' to count the number of divides. ⚠️ Heads up: Count may be incorrect When SMT is on. (yes, capital W "When", we don't ask questions 😭)

ARITH.MUL

(Event 14H, Umask 02H) — Counts the number of multiply operations executed. This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD. Count may be incorrect When SMT is on.

INST_QUEUE_WRITES

(Event 17H, Umask 01H) — Counts the number of instructions written into the instruction queue every cycle.

INST_DECODED.DEC0

(Event 18H, Umask 01H) — Counts number of instructions that require decoder 0 to be decoded. Usually, this means that the instruction maps to more than 1 uop. decoder 0 is carrying the team ngl

TWO_UOP_INSTS_DECODED

(Event 19H, Umask 01H) — An instruction that generates two uops was decoded.

INST_QUEUE_WRITE_CYCLES

(Event 1EH, Umask 01H) — This event counts the number of cycles during which instructions are written to the instruction queue. Dividing this counter by the number of instructions written to the instruction queue (INST_QUEUE_WRITES) yields the average number of instructions decoded each cycle. ✨ math ✨

If this number is less than four and the pipe stalls, this indicates that the decoder is failing to decode enough instructions per cycle to sustain the 4-wide pipeline. If SSE* instructions that are 6 bytes or longer arrive one after another, then front end throughput may limit execution speed. In such case,

okay so the original page literally just… stops there. "In such case," and then nothing. mid-sentence. not me leaving y'all on a cliffhanger 😭 that's genuinely how it is, i'm not hiding anything from you bestie 💀

LSD_OVERFLOW

(Event 20H, Umask 01H) — Counts number of loops that cant stream from the instruction queue. (their spelling, not mine 🎀)

L2_RQSTS.LD_HIT

(Event 24H, Umask 01H) — Counts number of loads that hit the L2 cache. L2 loads include both L1D demand misses as well as L1D prefetches. Note that L2 loads can be rejected for various reasons — only non rejected loads are counted. 🙈

L2_RQSTS.LD_MISS

(Event 24H, Umask 02H) — Counts the number of loads that miss the L2 cache. L2 loads include both L1D demand misses as well as L1D prefetches.

L2_RQSTS.LOADS

(Event 24H, Umask 03H) — Counts all L2 load requests. L2 loads include both L1D demand misses as well as L1D prefetches.

L2_RQSTS.RFO_HIT

(Event 24H, Umask 04H) — Counts the number of store RFO requests that hit the L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. Count includes WC memory requests, where the data is not fetched but the permission to write the line is required. 👀

L2_RQSTS.RFO_MISS

(Event 24H, Umask 08H) — Counts the number of store RFO requests that miss the L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.

L2_RQSTS.RFOS

(Event 24H, Umask 0CH) — Counts all L2 store RFO requests. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.

L2_RQSTS.IFETCH_HIT

(Event 24H, Umask 10H) — Counts number of instruction fetches that hit the L2 cache. L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches.

L2_RQSTS.IFETCH_MISS

(Event 24H, Umask 20H) — Counts number of instruction fetches that miss the L2 cache. L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches.

L2_RQSTS.IFETCHES

(Event 24H, Umask 30H) — Counts all instruction fetches. L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches.

L2_RQSTS.PREFETCH_HIT

(Event 24H, Umask 40H) — Counts L2 prefetch hits for both code and data.

L2_RQSTS.PREFETCH_MISS

(Event 24H, Umask 80H) — Counts L2 prefetch misses for both code and data.

L2_RQSTS.PREFETCHES

(Event 24H, Umask C0H) — Counts all L2 prefetches for both code and data.

L2_RQSTS.MISS

(Event 24H, Umask AAH) — Counts all L2 misses for both code and data.

L2_RQSTS.REFERENCES

(Event 24H, Umask FFH) — Counts all L2 requests for both code and data. the whole entire everything 💜

L2_DATA_RQSTS.DEMAND.I_STATE

(Event 26H, Umask 01H) — Counts number of L2 data demand loads where the cache line to be loaded is in the I (invalid) state, i.e. a cache miss. L2 demand loads are both L1D demand misses and L1D prefetches.

L2_DATA_RQSTS.DEMAND.S_STATE

(Event 26H, Umask 02H) — Counts number of L2 data demand loads where the cache line to be loaded is in the S (shared) state. L2 demand loads are both L1D demand misses and L1D prefetches.

L2_DATA_RQSTS.DEMAND.E_STATE

(Event 26H, Umask 04H) — Counts number of L2 data demand loads where the cache line to be loaded is in the E (exclusive) state. L2 demand loads are both L1D demand misses and L1D prefetches.

L2_DATA_RQSTS.DEMAND.M_STATE

(Event 26H, Umask 08H) — Counts number of L2 data demand loads where the cache line to be loaded is in the M (modified) state. L2 demand loads are both L1D demand misses and L1D prefetches.

L2_DATA_RQSTS.DEMAND.MESI

(Event 26H, Umask 0FH) — Counts all L2 data demand requests. L2 demand loads are both L1D demand misses and L1D prefetches.

L2_DATA_RQSTS.PREFETCH.I_STATE

(Event 26H, Umask 10H) — Counts number of L2 prefetch data loads where the cache line to be loaded is in the I (invalid) state, i.e. a cache miss.

L2_DATA_RQSTS.PREFETCH.S_STATE

(Event 26H, Umask 20H) — Counts number of L2 prefetch data loads where the cache line to be loaded is in the S (shared) state. Fun detail for the girlies: a prefetch RFO will miss on an S state line, while a prefetch read will hit on an S state line. 🦋

L2_DATA_RQSTS.PREFETCH.E_STATE

(Event 26H, Umask 40H) — Counts number of L2 prefetch data loads where the cache line to be loaded is in the E (exclusive) state.

L2_DATA_RQSTS.PREFETCH.M_STATE

(Event 26H, Umask 80H) — Counts number of L2 prefetch data loads where the cache line to be loaded is in the M (modified) state.

L2_DATA_RQSTS.PREFETCH.MESI

(Event 26H, Umask F0H) — Counts all L2 prefetch requests.

L2_DATA_RQSTS.ANY

(Event 26H, Umask FFH) — Counts all L2 data requests.

L2_WRITE.RFO.I_STATE

(Event 27H, Umask 01H) — Counts number of L2 demand store RFO requests where the cache line to be loaded is in the I (invalid) state, i.e, a cache miss. The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request. (note the comma after "i.e" — iconic, unchanged 💅)

L2_WRITE.RFO.S_STATE

(Event 27H, Umask 02H) — Counts number of L2 store RFO requests where the cache line to be loaded is in the S (shared) state. The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request.

L2_WRITE.RFO.M_STATE

(Event 27H, Umask 08H) — Counts number of L2 store RFO requests where the cache line to be loaded is in the M (modified) state. The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request.

L2_WRITE.RFO.HIT

(Event 27H, Umask 0EH) — Counts number of L2 store RFO requests where the cache line to be loaded is in either the S, E or M states. The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request. 🌸

  • L2_WRITE.RFO.MESI — (Event 27H, Umask 0FH) counts every single L2 store RFO request there is. Quick lil note bestie: the L1D prefetcher does not issue a RFO prefetch, so this is a demand RFO request. 💅
  • L2_WRITE.LOCK.I_STATE — (Event 27H, Umask 10H) counts the L2 demand lock RFO requests where the cache line about to be loaded is sitting in the I (invalid) state — which is just a fancy way of saying the read request missed the cache. 😭
  • L2_WRITE.LOCK.S_STATE — (Event 27H, Umask 20H) counts the L2 lock RFO requests where the cache line to be loaded is in the S (shared) state. 🫶
  • L2_WRITE.LOCK.E_STATE — (Event 27H, Umask 40H) counts the L2 demand lock RFO requests where the cache line to be loaded is in the E (exclusive) state. ✨
  • L2_WRITE.LOCK.M_STATE — (Event 27H, Umask 80H) counts the L2 demand lock RFO requests where the cache line to be loaded is in the M (modified) state. 🦋
  • L2_WRITE.LOCK.HIT — (Event 27H, Umask E0H) counts the L2 demand lock RFO requests where the cache line to be loaded is in either the S, E, or M state — so, the whole "hit club," basically the it-girls of cache states. 👑
  • L2_WRITE.LOCK.MESI — (Event 27H, Umask F0H) counts all L2 demand lock RFO requests. every last one, no cap. 🔥
  • L1D_WB_L2.I_STATE — (Event 28H, Umask 01H) counts the L1 writebacks to the L2 where the cache line to be written is in the I (invalid) state, i.e. a cache miss. 💀
  • L1D_WB_L2.S_STATE — (Event 28H, Umask 02H) counts the L1 writebacks to the L2 where the cache line to be written is in the S state. 🌸
  • L1D_WB_L2.E_STATE — (Event 28H, Umask 04H) counts the L1 writebacks to the L2 where the cache line to be written is in the E (exclusive) state. ⭐
  • L1D_WB_L2.M_STATE — (Event 28H, Umask 08H) counts the L1 writebacks to the L2 where the cache line to be written is in the M (modified) state. 🎀
  • L1D_WB_L2.MESI — (Event 28H, Umask 0FH) counts all L1 writebacks to the L2. the whole parade. 🌈
  • L3_LAT_CACHE.REFERENCE — (Event 2EH, Umask 4FH) counts requests coming from the core that reference a cache line in the last level cache. The count includes speculative traffic but excludes cache line fills due to a L2 hardware-prefetch. And because cache hierarchy, cache sizes and other implementation-specific characteristics exist — value comparison to estimate performance differences is not recommended. see Table A-1. 🙈
  • L3_LAT_CACHE.MISS — (Event 2EH, Umask 41H) counts each cache miss condition for references to the last level cache. The count may include speculative traffic but excludes cache line fills due to L2 hardware-prefetches. Same warning bestie: because cache hierarchy, cache sizes and other implementation-specific characteristics — value comparison to estimate performance differences is not recommended. see Table A-1. 😭
  • CPU_CLK_UNHALTED.THREAD_P — (Event 3CH, Umask 00H) counts the number of thread cycles while the thread is not in a halt state. A thread enters the halt state when it's running the HLT instruction. Heads up: the core frequency may change from time to time due to power or thermal throttling. 🔥 see Table A-1.
  • CPU_CLK_UNHALTED.REF_P — (Event 3CH, Umask 01H) increments at the frequency of TSC when not halted. see Table A-1. ⏰
  • L1D_CACHE_LD.I_STATE — (Event 40H, Umask 01H) counts L1 data cache read requests where the cache line to be loaded is in the I (invalid) state — i.e. the read request missed the cache. Counter 0, 1 only. 💅
  • L1D_CACHE_LD.S_STATE — (Event 40H, Umask 02H) counts L1 data cache read requests where the cache line to be loaded is in the S (shared) state. Counter 0, 1 only. 🌸
  • L1D_CACHE_LD.E_STATE — (Event 40H, Umask 04H) counts L1 data cache read requests where the cache line to be loaded is in the E (exclusive) state. Counter 0, 1 only. ✨
  • L1D_CACHE_LD.M_STATE — (Event 40H, Umask 08H) counts L1 data cache read requests where the cache line to be loaded is in the M (modified) state. Counter 0, 1 only. 🦋
  • L1D_CACHE_LD.MESI — (Event 40H, Umask 0FH) counts L1 data cache read requests, periodt. Counter 0, 1 only. 👑
  • L1D_CACHE_ST.S_STATE — (Event 41H, Umask 02H) counts L1 data cache store RFO requests where the cache line to be loaded is in the S (shared) state. Counter 0, 1 only. 🫶
  • L1D_CACHE_ST.E_STATE — (Event 41H, Umask 04H) counts L1 data cache store RFO requests where the cache line to be loaded is in the E (exclusive) state. Counter 0, 1 only. ⭐
  • L1D_CACHE_ST.M_STATE — (Event 41H, Umask 08H) counts L1 data cache store RFO requests where the cache line to be loaded is in the M (modified) state. Counter 0, 1 only. 🎀
  • L1D_CACHE_LOCK.HIT — (Event 42H, Umask 01H) counts retired load locks that hit in the L1 data cache or hit in an already allocated fill buffer. The lock portion of the load lock transaction must hit in the L1D — and the initial load will pull the lock into the L1 data cache. Counter 0, 1 only. 💖
  • L1D_CACHE_LOCK.S_STATE — (Event 42H, Umask 02H) counts L1 data cache retired load locks that hit the target cache line in the shared state. Counter 0, 1 only. 🌸
  • L1D_CACHE_LOCK.E_STATE — (Event 42H, Umask 04H) counts L1 data cache retired load locks that hit the target cache line in the exclusive state. Counter 0, 1 only. ✨
  • L1D_CACHE_LOCK.M_STATE — (Event 42H, Umask 08H) counts L1 data cache retired load locks that hit the target cache line in the modified state. Counter 0, 1 only. 🦋
  • L1D_ALL_REF.ANY — (Event 43H, Umask 01H) counts all references — uncached, speculated and retired — to the L1 data cache, including all loads and stores with any memory types. Important detail: the event counts memory accesses only when they're actually performed. For example, a load blocked by an unknown store address and later performed is only counted once. And it does not include non-memory accesses, such as I/O accesses. Counter 0, 1 only. 😭
  • L1D_ALL_REF.CACHEABLE — (Event 43H, Umask 02H) counts all data reads and writes (speculated and retired) from cacheable memory, including locked operations. Counter 0, 1 only. 🔥
  • DTLB_MISSES.ANY — (Event 49H, Umask 01H) counts the number of misses in the STLB which cause a page walk. 🚶‍♀️
  • DTLB_MISSES.WALK_COMPLETED — (Event 49H, Umask 02H) counts the number of misses in the STLB which resulted in a completed page walk. ✅
  • DTLB_MISSES.STLB_HIT — (Event 49H, Umask 10H) counts the number of DTLB first level misses that hit in the second level TLB. Heads up: this event is only relevant if the core contains multiple DTLB levels. 👀
  • DTLB_MISSES.PDE_MISS — (Event 49H, Umask 20H) is the number of DTLB misses caused by the low part of the address, and it includes references to 2M pages because 2M pages do not use the PDE. 🧚
  • DTLB_MISSES.LARGE_WALK_COMPLETED — (Event 49H, Umask 80H) counts the number of misses in the STLB which resulted in a completed page walk for large pages. 🌈
  • LOAD_HIT_PRE — (Event 4CH, Umask 01H) counts load operations sent to the L1 data cache while a previous SSE prefetch instruction to the same cache line has started prefetching but has not yet finished. the in-between era. 🫶
  • L1D_PREFETCH.REQUESTS — (Event 4EH, Umask 01H) counts the number of hardware prefetch requests dispatched out of the prefetch FIFO. 📤
  • L1D_PREFETCH.MISS — (Event 4EH, Umask 02H) counts the number of hardware prefetch requests that miss the L1D. Quick lore drop: there are two prefetchers in the L1D — a streamer, which predicts lines sequentially after this one should be fetched, and the IP prefetcher that remembers access patterns for the current instruction. The streamer prefetcher stops on an L1D hit, while the IP prefetcher does not. 💀
  • L1D_PREFETCH.TRIGGERS — (Event 4EH, Umask 04H) counts the number of prefetch requests triggered by the Finite State Machine and pushed into the prefetch FIFO. Some of these prefetch requests get dropped due to overwrites or competition between the IP index prefetcher and streamer prefetcher. Fun fact: the prefetch FIFO contains 4 entries. 🎀
  • L1D.REPL — (Event 51H, Umask 01H) counts the number of lines brought into the L1 data cache. Counter 0, 1 only. 🌸
  • L1D.M_REPL — (Event 51H, Umask 02H) counts the number of modified lines brought into the L1 data cache. Counter 0, 1 only. ✨
  • L1D.M_EVICT — (Event 51H, Umask 04H) counts the number of modified lines evicted from the L1 data cache due to replacement. Counter 0, 1 only. 😭
  • L1D.M_SNOOP_EVICT — (Event 51H, Umask 08H) counts the number of modified lines evicted from the L1 data cache due to snoop HITM intervention. Counter 0, 1 only. 💀
  • L1D_CACHE_PREFETCH_LOCK_FB_HIT — (Event 52H, Umask 01H) counts the number of cacheable load lock speculated instructions accepted into the fill buffer. 💖
  • L1D_CACHE_LOCK_FB_HIT — (Event 53H, Umask 01H) counts the number of cacheable load lock speculated or retired instructions accepted into the fill buffer. 🫶
  • CACHE_LOCK_CYCLES.L1D_L2 — (Event 63H, Umask 01H) is the cycle count during which the L1D and L2 are locked. A lock is asserted when there's a locked memory access, due to uncacheable memory, a locked operation that spans two cache lines, or a page walk from an uncacheable page table. Counter 0, 1 only. 🚨 Real talk: L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such accesses. not the vibe, avoid. 🙈
  • CACHE_LOCK_CYCLES.L1D — (Event 63H, Umask 02H) counts the number of cycles that the cacheline in the L1 data cache unit is locked. Counter 0, 1 only. 🔒
  • IO_TRANSACTIONS — (Event 6CH, Umask 01H) counts the number of completed I/O transactions. done and dusted. ✅
  • L1I.HITS — (Event 80H, Umask 01H) counts all instruction fetches that hit the L1 instruction cache. every single one, iconic. 👑✨
  • L1I.MISSES — (Event 80H, Umask 02H) Counts all the instruction fetches that miss the L1I cache 💅 that means instruction cache misses, streaming buffer misses, victim cache misses and uncacheable fetches all get counted. And bestie, listen: an instruction fetch miss gets counted once, not once for every cycle it's sitting there outstanding. No double-dipping, periodt.
  • L1I.READS — (Event 80H, Umask 03H) Counts every single instruction fetch, and yes that includes the uncacheable fetches that straight-up bypass the L1I 🙈
  • L1I.CYCLES_STALLED — (Event 80H, Umask 04H) Cycle counts for when an instruction fetch stalls because of a L1I cache miss, an ITLB miss, or an ITLB fault. It's giving "stuck in traffic" energy 😭
  • LARGE_ITLB.HIT — (Event 82H, Umask 01H) Counts how many large ITLB hits happen. Slay.
  • ITLB_MISSES.ANY — (Event 85H, Umask 01H) Counts the number of misses in all levels of the ITLB that cause a page walk 🚶‍♀️
  • ITLB_MISSES.WALK_COMPLETED — (Event 85H, Umask 02H) Counts the number of misses in all levels of the ITLB that resulted in a completed page walk ✨
  • ILD_STALL.LCP — (Event 87H, Umask 01H) Cycles the Instruction Length Decoder stalls because of length-changing prefixes: 66, 67, or REX.W (for EM64T) instructions that change the length of the decoded instruction. Iconic little troublemakers.
  • ILD_STALL.MRU — (Event 87H, Umask 02H) Instruction Length Decoder stall cycles caused by the Brand Prediction Unit (PBU) Most Recently Used (MRU) bypass.
  • ILD_STALL.IQ_FULL — (Event 87H, Umask 04H) Stall cycles because the instruction queue is full. Too many girlies in the queue, no cap 💀
  • ILD_STALL.REGEN — (Event 87H, Umask 08H) Counts the number of regen stalls.
  • ILD_STALL.ANY — (Event 87H, Umask 0FH) Counts any cycles where the Instruction Length Decoder is stalled. The catch-all bestie 🫶
  • BR_INST_EXEC.COND — (Event 88H, Umask 01H) Counts the number of conditional near branch instructions executed — but not necessarily retired, iykyk.
  • BR_INST_EXEC.DIRECT — (Event 88H, Umask 02H) Counts all unconditional near branch instructions, excluding calls and indirect branches.
  • BR_INST_EXEC.INDIRECT_NON_CALL — (Event 88H, Umask 04H) Counts the number of executed indirect near branch instructions that are not calls.
  • BR_INST_EXEC.NON_CALLS — (Event 88H, Umask 07H) Counts all non-call near branch instructions executed, but not necessarily retired.
  • BR_INST_EXEC.RETURN_NEAR — (Event 88H, Umask 08H) Counts indirect near branches that have a return mnemonic. Coming back like a boomerang 🪃
  • BR_INST_EXEC.DIRECT_NEAR_CALL — (Event 88H, Umask 10H) Counts unconditional near call branch instructions executed, excluding non-call branches.
  • BR_INST_EXEC.INDIRECT_NEAR_CALL — (Event 88H, Umask 20H) Counts indirect near calls executed — both register indirect and memory indirect 🎀
  • BR_INST_EXEC.NEAR_CALLS — (Event 88H, Umask 30H) Counts all near call branches executed, but not necessarily retired.
  • BR_INST_EXEC.TAKEN — (Event 88H, Umask 40H) Counts taken near branches executed, but not necessarily retired. Taken, like, obviously 💅
  • BR_INST_EXEC.ANY — (Event 88H, Umask 7FH) Counts all near executed branches (not necessarily retired). Heads up: this includes only instructions, not micro-op branches. And ngl — frequent branching is not necessarily a major performance issue, but frequent branch mispredictions may be a problem 👀
  • BR_MISP_EXEC.COND — (Event 89H, Umask 01H) Counts the number of mispredicted conditional near branch instructions executed, but not necessarily retired.
  • BR_MISP_EXEC.DIRECT — (Event 89H, Umask 02H) Counts mispredicted macro unconditional near branch instructions, excluding calls and indirect branches — and bestie, this one should always be 0 🙈
  • BR_MISP_EXEC.INDIRECT_NON_CALL — (Event 89H, Umask 04H) Counts the number of executed mispredicted indirect near branch instructions that are not calls.
  • BR_MISP_EXEC.NON_CALLS — (Event 89H, Umask 07H) Counts mispredicted non-call near branches executed, but not necessarily retired.
  • BR_MISP_EXEC.RETURN_NEAR — (Event 89H, Umask 08H) Counts mispredicted indirect branches that have a rear return mnemonic.
  • BR_MISP_EXEC.DIRECT_NEAR_CALL — (Event 89H, Umask 10H) Counts mispredicted non-indirect near calls executed — and again, this should always be 0 😭
  • BR_MISP_EXEC.INDIRECT_NEAR_CALL — (Event 89H, Umask 20H) Counts mispredicted indirect near calls executed, including both register and memory indirect.
  • BR_MISP_EXEC.NEAR_CALLS — (Event 89H, Umask 30H) Counts all mispredicted near call branches executed, but not necessarily retired.
  • BR_MISP_EXEC.TAKEN — (Event 89H, Umask 40H) Counts executed mispredicted near branches that are taken, but not necessarily retired.
  • BR_MISP_EXEC.ANY — (Event 89H, Umask 7FH) Counts the number of mispredicted near branch instructions that were executed, but not necessarily retired. The whole misprediction cinematic universe 🌈
  • RESOURCE_STALLS.ANY — (Event A2H, Umask 01H) Counts the number of Allocator resource-related stalls. Includes register renaming buffer entries and memory buffer entries. On top of the resource-related stalls, this also counts some other events — including stalls that pop up during branch misprediction recovery, like when retirement of the mispredicted branch is delayed, and stalls that happen while the store buffer is draining from synchronizing operations. What it does not include: stalls due to SuperQ (off-core) queue full, too many cache misses, etc. So don't come for it about those 💀
  • RESOURCE_STALLS.LOAD — (Event A2H, Umask 02H) Counts the cycles of stall due to a lack of load buffer for a load operation.
  • RESOURCE_STALLS.RS_FULL — (Event A2H, Umask 04H) Counts the number of cycles when the number of instructions in the pipeline waiting for execution reaches the limit the processor can handle. A high count of this event means there are long-latency operations in the pipe — possibly load and store operations that miss the L2 cache, or instructions dependent on instructions further down the pipeline that have yet to retire. When the RS is full, new instructions cannot enter the reservation station and start execution. It's giving "club's at capacity" 🚫
  • RESOURCE_STALLS.STORE — (Event A2H, Umask 08H) Counts the number of cycles where a resource-related stall will occur because the number of store instructions reached the pipeline's limit — i.e. all store buffers are used. The stall ends when a store instruction commits its data to the cache or memory. Closure 💅
  • RESOURCE_STALLS.ROB_FULL — (Event A2H, Umask 10H) Counts the cycles of stall due to the re-order buffer being full.
  • RESOURCE_STALLS.FPCW — (Event A2H, Umask 20H) Counts the number of cycles while execution was stalled due to writing the floating-point unit (FPU) control word.
  • RESOURCE_STALLS.MXCSR — (Event A2H, Umask 40H) Stalls due to the MXCSR register rename occurring too close to a previous MXCSR rename. Just so you know, the MXCSR provides control and status for the MMX registers ✨
  • RESOURCE_STALLS.OTHER — (Event A2H, Umask 80H) Counts the number of cycles while execution was stalled due to other resource issues. The miscellaneous era 🎀
  • MACRO_INSTS.FUSIONS_DECODED — (Event A6H, Umask 01H) Counts the number of instructions decoded that are macro-fused — but not necessarily executed or retired. Decoded ≠ done, bestie.
  • BACLEAR_FORCE_IQ — (Event A7H, Umask 01H) Counts the number of times a BACLEAR was forced by the Instruction Queue. So here's the lore: the IQ is also responsible for providing conditional branch prediction direction based on a static scheme and dynamic data provided by the L2 Branch Prediction Unit. If the conditional branch target isn't found in the Target Array and the IQ predicts that the branch is taken, then the IQ will force the Branch Address Calculator to issue a BACLEAR. Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble in the instruction fetch pipeline 😭 eight whole cycles, gone.
  • LSD.UOPS — (Event A8H, Umask 01H) Counts the number of micro-ops delivered by the loop stream detector. Use cmask=1 and invert to count cycles.
  • ITLB_FLUSH — (Event AEH, Umask 01H) Counts the number of ITLB flushes 🚽 (jk, but it is a flush)
  • OFFCORE_REQUESTS.L1D_WRITEBACK — (Event B0H, Umask 40H) Counts the number of L1D writebacks to the uncore.
  • UOPS_EXECUTED.PORT0 — (Event B1H, Umask 01H) Counts the number of Uops executed that were issued on port 0. Port 0 handles integer arithmetic, SIMD and FP add Uops. Busy girl 💅
  • UOPS_EXECUTED.PORT1 — (Event B1H, Umask 02H) Counts the number of Uops executed that were issued on port 1. Port 1 handles integer arithmetic, SIMD, integer shift, FP multiply and FP divide Uops. She does it all 👑
  • UOPS_EXECUTED.PORT2_CORE — (Event B1H, Umask 04H) Counts the number of Uops executed that were issued on port 2. Port 2 handles the load Uops. Heads up: this is a core count only and can not be collected per thread 🙅‍♀️
  • UOPS_EXECUTED.PORT3_CORE — (Event B1H, Umask 08H) Counts the number of Uops executed that were issued on port 3. Port 3 handles store Uops. Again — core count only, can not be collected per thread.
  • UOPS_EXECUTED.PORT4_CORE — (Event B1H, Umask 10H) Counts the number of Uops executed that were issued on port 4. Port 4 handles the value to be stored for the store Uops issued on port 3. And yep — core count only, can not be collected per thread.
  • UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5 — (Event B1H, Umask 1FH) Counts cycles when the Uops executed were issued from any ports except port 5. Bestie, the knob situation: use Cmask=1 for active cycles; Cmask=0 for weighted cycles; use CMask=1, Invert=1 to count P0-4 stalled cycles; use Cmask=1, Edge=1, Invert=1 to count P0-4 stalls.
  • UOPS_EXECUTED.PORT5 — (Event B1H, Umask 20H) Counts the number of Uops executed that were issued on port 5. The one that got left out of the last event, we love her 🫶
  • UOPS_EXECUTED.CORE_ACTIVE_CYCLES — (Event B1H, Umask 3FH) Counts cycles when the Uops are executing. Same knob drill: use Cmask=1 for active cycles; Cmask=0 for weighted cycles; use CMask=1, Invert=1 to count P0-4 stalled cycles; use Cmask=1, Edge=1, Invert=1 to count P0-4 stalls.
  • UOPS_EXECUTED.PORT015 — (Event B1H, Umask 40H) counts how many uops got executed that were issued on port 0, 1, or 5. bestie if you wanna count stall cycles instead, use cmask=1, invert=1 💅
  • UOPS_EXECUTED.PORT234 — (Event B1H, Umask 80H) counts the number of uops executed that were issued on port 2, 3, or 4. slay.
  • OFFCORE_REQUESTS_SQ_FULL — (Event B2H, Umask 01H) counts the number of cycles the SQ is full and can't handle off-core requests. it's giving "line out the door" energy 😭
  • OFF_CORE_RESPONSE_0 — (Event B7H, Umask 01H) see Section 30.6.1.3, Off-core Response Performance Monitoring in the Processor Core. ⚠️ requires programming MSR 01A6H — no cap, you gotta set that up first.
  • SNOOP_RESPONSE.HIT — (Event B8H, Umask 01H) counts HIT snoop responses sent by this thread in response to a snoop request. 🦋
  • SNOOP_RESPONSE.HITE — (Event B8H, Umask 02H) counts HIT E snoop responses sent by this thread in response to a snoop request. ✨
  • SNOOP_RESPONSE.HITM — (Event B8H, Umask 04H) counts HIT M snoop responses sent by this thread in response to a snoop request. 🔥
  • OFF_CORE_RESPONSE_1 — (Event BBH, Umask 01H) see Section 30.6.1.3, Off-core Response Performance Monitoring in the Processor Core. ⚠️ this one needs MSR 01A7H programmed — different MSR than the _0 one, don't mix them up bestie 🙈
  • INST_RETIRED.ANY_P — (Event C0H, Umask 01H) see Table A-1. Notes, and these matter: INST_RETIRED.ANY is counted by a designated fixed counter, while INST_RETIRED.ANY_P is counted by a programmable counter and is an architectural performance event. it's supported if CPUID.A.EBX[1] = 0. Counting deets: faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions. periodt 💅
  • INST_RETIRED.X87 — (Event C0H, Umask 02H) counts the number of MMX instructions retired. yes, that's what the original says, we're not gonna question it, we're just reporting it 🫶
  • INST_RETIRED.MMX — (Event C0H, Umask 04H) counts the number of floating point computational operations retired — specifically floating point computational operations executed by the assist handler, plus sub-operations of complex floating point instructions like transcendental instructions. 🧚
  • UOPS_RETIRED.ANY — (Event C2H, Umask 01H) counts the number of micro-ops retired (macro-fused=1, micro-fused=2, others =1; maximum count of 8 per cycle). most instructions are composed of one or two micro-ops — some instructions get decoded into longer sequences, like repeat instructions, floating point transcendental instructions, and assists. use cmask=1 and invert to count active cycles or stalled cycles. 💜
  • UOPS_RETIRED.RETIRE_SLOTS — (Event C2H, Umask 02H) counts the number of retirement slots used each cycle. iconic. 🌈
  • UOPS_RETIRED.MACRO_FUSED — (Event C2H, Umask 04H) counts the number of macro-fused uops retired. 🎀
  • MACHINE_CLEARS.CYCLES — (Event C3H, Umask 01H) counts the cycles machine clear is asserted. 💀
  • MACHINE_CLEARS.MEM_ORDER — (Event C3H, Umask 02H) counts the number of machine clears due to memory order conflicts. your pipeline said "nope" fr fr 😭
  • MACHINE_CLEARS.SMC — (Event C3H, Umask 04H) counts the number of times a program writes to a code section. and listen — self-modifying code causes a severe penalty in all Intel 64 and IA-32 processors. the modified cache line gets written back to the L2 and L3 caches. so like, don't do that 💀
  • BR_INST_RETIRED.ALL_BRANCHES — (Event C4H, Umask 00H) see Table A-1. 👑
  • BR_INST_RETIRED.CONDITIONAL — (Event C4H, Umask 01H) counts the number of conditional branch instructions retired. the "if bestie then bestie else bestie" of instructions 🌸
  • BR_INST_RETIRED.NEAR_CALL — (Event C4H, Umask 02H) counts the number of direct & indirect near unconditional calls retired. 🫶
  • BR_INST_RETIRED.ALL_BRANCHES — (Event C4H, Umask 04H) counts the number of branch instructions retired. (yes it's listed again with a different umask — that's how the original rolls, I don't make the rules ✨)
  • BR_MISP_RETIRED.ALL_BRANCHES — (Event C5H, Umask 00H) see Table A-1. 💅
  • BR_MISP_RETIRED.NEAR_CALL — (Event C5H, Umask 02H) counts mispredicted direct & indirect near unconditional retired calls. the predictor fumbled the bag 🙈
  • SSEX_UOPS_RETIRED.PACKED_SINGLE — (Event C7H, Umask 01H) counts SIMD packed single-precision floating point Uops retired. 🍓
  • SSEX_UOPS_RETIRED.SCALAR_SINGLE — (Event C7H, Umask 02H) counts SIMD scalar single-precision floating point Uops retired. (sic — the original literally says "SIMD calar", we're keeping the typo energy alive 😭)
  • SSEX_UOPS_RETIRED.PACKED_DOUBLE — (Event C7H, Umask 04H) counts SIMD packed double-precision floating point Uops retired. ✨
  • SSEX_UOPS_RETIRED.SCALAR_DOUBLE — (Event C7H, Umask 08H) counts SIMD scalar double-precision floating point Uops retired. 💜
  • SSEX_UOPS_RETIRED.VECTOR_INTEGER — (Event C7H, Umask 10H) counts 128-bit SIMD vector integer Uops retired. highkey a vibe 🔥
  • ITLB_MISS_RETIRED — (Event C8H, Umask 20H) counts the number of retired instructions that missed the ITLB when the instruction was fetched. 🦋
  • MEM_LOAD_RETIRED.L1D_HIT — (Event CBH, Umask 01H) counts the number of retired loads that hit the L1 data cache. the cozy short trip 💖
  • MEM_LOAD_RETIRED.L2_HIT — (Event CBH, Umask 02H) counts the number of retired loads that hit the L2 data cache. ✨
  • MEM_LOAD_RETIRED.L3_UNSHARED_HIT — (Event CBH, Umask 04H) counts the number of retired loads that hit their own, unshared lines in the L3 cache. no sharing, main character energy 👑
  • MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM — (Event CBH, Umask 08H) counts the number of retired loads that hit in a sibling core's L2 (on die core). since the L3 is inclusive of all cores on the package, this counts as an L3 hit — and it counts both clean or modified hits. 🫶
  • MEM_LOAD_RETIRED.L3_MISS — (Event CBH, Umask 10H) counts the number of retired loads that miss the L3 cache. the load was satisfied by a remote socket, local memory, or an IOH. long-distance relationship vibes 😭
  • MEM_LOAD_RETIRED.HIT_LFB — (Event CBH, Umask 40H) counts the number of retired loads that miss the L1D and whose address is located in an allocated line fill buffer and will soon be committed to cache. this is counting secondary L1D misses. 🌸
  • MEM_LOAD_RETIRED.DTLB_MISS — (Event CBH, Umask 80H) counts the number of retired loads that missed the DTLB. a few caveats, bestie, pay attention: the DTLB miss is not counted if the load operation causes a fault; this event counts loads from cacheable memory only; the event does not count loads by software prefetches; and it counts both primary and secondary misses to the TLB. 📝
  • FP_MMX_TRANS.TO_FP — (Event CCH, Umask 01H) counts the first floating-point instruction following any MMX instruction. you can use this event to estimate the penalties for the transitions between floating-point and MMX technology states. 💅
  • FP_MMX_TRANS.TO_MMX — (Event CCH, Umask 02H) counts the first MMX instruction following a floating-point instruction. same deal — you can use this event to estimate the penalties for the transitions between floating-point and MMX technology states. 🔄
  • FP_MMX_TRANS.ANY — (Event CCH, Umask 03H) counts all transitions from floating point to MMX instructions and from MMX instructions to floating point instructions. and yes, you can use this event to estimate the penalties for the transitions between floating-point and MMX technology states. it's the both-ways bestie 🌈
  • MACRO_INSTS.DECODED — (Event D0H, Umask 01H) counts the number of instructions decoded (but not necessarily executed or retired). decoded ≠ did the thing, iykyk 🙈
  • UOPS_DECODED.MS — (Event D1H, Umask 02H) counts the number of Uops decoded by the Microcode Sequencer, MS. the MS delivers uops when the instruction is more than 4 uops long or a microcode assist is occurring. 🧚
  • UOPS_DECODED.ESP_FOLDING — (Event D1H, Umask 04H) counts the number of stack pointer (ESP) instructions decoded: push, pop, call, ret, etc. ESP instructions do not generate a Uop to increment or decrement ESP — instead, they update an ESP_Offset register that keeps track of the delta to the current value of the ESP register. so efficient, we love that 💅
  • UOPS_DECODED.ESP_SYNC — (Event D1H, Umask 08H) counts the number of stack pointer (ESP) sync operations, where an ESP instruction is corrected by adding the ESP offset register to the current value of the ESP register. 🎀
  • RAT_STALLS.FLAGS — (Event D2H, Umask 01H) counts the number of cycles during which execution stalled due to several reasons, one of which is a partial flag register stall. a partial register stall may occur when two conditions are met: 1) an instruction modifies some, but not all, of the flags in the flag register, and 2) the next instruction, which depends on flags, depends on flags that were not modified by this instruction. half-updated flags = chaos 😭
  • RAT_STALLS.REGISTERS — (Event D2H, Umask 02H) this event counts the number of cycles instruction execution latency became longer than the defined latency, because the instruction used a register that was partially written by a previous instruction. 🫶
  • RAT_STALLS.ROB_READ_PORT — (Event D2H, Umask 04H) counts the number of cycles when ROB read port stalls occurred, which did not allow new micro-ops to enter the out-of-order pipeline. 📝 heads up though: at this stage in the pipeline, additional stalls may occur at the same cycle and prevent the stalled micro-ops from entering the pipe — in that case, micro-ops retry entering the execution pipe in the next cycle and the ROB-read port stall is counted again. 🔁
  • RAT_STALLS.SCOREBOARD — (Event D2H, Umask 08H) counts the cycles where we stall due to microarchitecturally required serialization. microcode scoreboarding stalls. it's giving "waiting for the group chat to agree" 💀
  • RAT_STALLS.ANY — (Event D2H, Umask 0FH) counts all Register Allocation Table stall cycles due to: cycles when ROB read port stalls occurred, which did not allow new micro-ops to enter the execution pipe; cycles when partial register stalls occurred; cycles when flag stalls occurred; and cycles when floating-point unit (FPU) status word stalls occurred. 💖 to count each of these conditions separately, use the events: RAT_STALLS.ROB_READ_PORT, RAT_STALLS.PARTIAL, RAT_STALLS.FLAGS, and RAT_STALLS.FPSW.
  • SEG_RENAME_STALLS — (Event D4H, Umask 01H) counts the stall cycles you eat because there just aren't enough renaming resources for the ES, DS, FS, and GS segment registers 😭. Like, if a segment gets renamed but isn't retired yet and then a second update to that same segment shows up, the front-end of the pipeline just stalls out until the renamed segment retires. rip.
  • ES_REG_RENAMES — (Event D5H, Umask 01H) counts how many times the ES segment register gets renamed ✨.
  • UOP_UNFUSION — (Event DBH, Umask 01H) counts unfusion events caused by a floating point exception hitting a fused uop 💅.
  • BR_INST_DECODED — (Event E0H, Umask 01H) counts the branch instructions that got decoded 🌸.
  • BPU_MISSED_CALL_RET — (Event E5H, Umask 01H) counts the times the Branch Prediction Unit fumbled predicting a call or a return branch 🙈.
  • BACLEAR.CLEAR — (Event E6H, Umask 01H) counts how often the front end gets resteered — mostly when the Branch Prediction Unit can't give a correct prediction and the Branch Address Calculator at the front end has to come in and fix it 🫶. This can happen when the code has so many branches that the BPU can't consume them all. Every BACLEAR asserted by the BAC generates roughly an 8 cycle bubble in the instruction fetch pipeline, and the effect on total execution time depends on the surrounding code. iykyk.
  • BACLEAR.BAD_TARGET — (Event E6H, Umask 02H) counts the Branch Address Calculator clears (BACLEAR) asserted because of conditional branch instructions where there was a target hit but the direction was wrong 💀. Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble in the instruction fetch pipeline.
  • BPU_CLEARS.EARLY — (Event E8H, Umask 01H) counts early (normal) Branch Prediction Unit clears: the BPU predicted a taken branch after incorrectly assuming it was not taken 😬. That clear leads to a 2 cycle bubble in the Front End.
  • BPU_CLEARS.LATE — (Event E8H, Umask 02H) counts late Branch Prediction Unit clears due to Most Recently Used conflicts. The PBU clear leads to a 3 cycle bubble in the Front End.
  • L2_TRANSACTIONS.LOAD — (Event F0H, Umask 01H) counts L2 load operations from HW prefetch or demand loads 🦋.
  • L2_TRANSACTIONS.RFO — (Event F0H, Umask 02H) counts L2 RFO operations from HW prefetch or demand RFOs.
  • L2_TRANSACTIONS.IFETCH — (Event F0H, Umask 04H) counts L2 instruction fetch operations from HW prefetch or demand ifetch.
  • L2_TRANSACTIONS.PREFETCH — (Event F0H, Umask 08H) counts L2 prefetch operations.
  • L2_TRANSACTIONS.L1D_WB — (Event F0H, Umask 10H) counts L1D writeback operations going to the L2.
  • L2_TRANSACTIONS.FILL — (Event F0H, Umask 20H) counts L2 cache line fill operations from loads, RFO, L1D writeback or prefetch 📥.
  • L2_TRANSACTIONS.WB — (Event F0H, Umask 40H) counts L2 writeback operations going to the L3.
  • L2_TRANSACTIONS.ANY — (Event F0H, Umask 80H) counts, like, all the L2 cache operations 👑.
  • L2_LINES_IN.S_STATE — (Event F1H, Umask 02H) counts the cache lines allocated in the L2 cache in the S (shared) state.
  • L2_LINES_IN.E_STATE — (Event F1H, Umask 04H) counts the cache lines allocated in the L2 cache in the E (exclusive) state.
  • L2_LINES_IN.ANY — (Event F1H, Umask 07H) counts the cache lines allocated in the L2 cache. full stop.
  • L2_LINES_OUT.DEMAND_CLEAN — (Event F2H, Umask 01H) counts L2 clean cache lines evicted by a demand request 🧹.
  • L2_LINES_OUT.DEMAND_DIRTY — (Event F2H, Umask 02H) counts L2 dirty (modified) cache lines evicted by a demand request.
  • L2_LINES_OUT.PREFETCH_CLEAN — (Event F2H, Umask 04H) counts L2 clean cache lines evicted by a prefetch request.
  • L2_LINES_OUT.PREFETCH_DIRTY — (Event F2H, Umask 08H) counts L2 modified cache lines evicted by a prefetch request.
  • L2_LINES_OUT.ANY — (Event F2H, Umask 0FH) counts every single L2 cache line evicted, no matter the reason 💅.
  • SQ_MISC.SPLIT_LOCK — (Event F4H, Umask 10H) counts the number of SQ lock splits across a cache line.
  • SQ_FULL_STALL_CYCLES — (Event F6H, Umask 01H) counts the cycles where the Super Queue is full 😭. When that happens, neither of the threads on this core can access the uncore. not one. not the other. rough.
  • FP_ASSIST.ALL — (Event F7H, Umask 01H) counts the floating point operations that needed micro-code assist intervention 🔥. Assists are required in these cases: SSE instructions, (Denormal input when the DAZ flag is off or Underflow result when the FTZ flag is off); x87 instructions, (NaN or denormal are loaded to a register or used as input from memory, Division by 0 or Underflow output).
  • FP_ASSIST.OUTPUT — (Event F7H, Umask 02H) counts the floating point micro-code assists where the output value (destination register) is invalid.
  • FP_ASSIST.INPUT — (Event F7H, Umask 04H) counts the floating point micro-code assists where the input value (one of the source operands to an FP instruction) is invalid.
  • SIMD_INT_64.PACKED_MPY — (Event FDH, Umask 01H) counts SID integer 64 bit packed multiply operations ✨.
  • SIMD_INT_64.PACKED_SHIFT — (Event FDH, Umask 02H) counts SID integer 64 bit packed shift operations.
  • SIMD_INT_64.PACK — (Event FDH, Umask 04H) counts SID integer 64 bit pack operations.
  • SIMD_INT_64.UNPACK — (Event FDH, Umask 08H) counts SID integer 64 bit unpack operations.
  • SIMD_INT_64.PACKED_LOGICAL — (Event FDH, Umask 10H) counts SID integer 64 bit logical operations.
  • SIMD_INT_64.PACKED_ARITH — (Event FDH, Umask 20H) counts SID integer 64 bit arithmetic operations.
  • SIMD_INT_64.SHUFFLE_MOVE — (Event FDH, Umask 40H) counts SID integer 64 bit shift or move operations.

🌈 Event Specifiers (Programmable PMCs) 🌈

Core i7 and Xeon 5500 programmable PMCs support the following events as the June 2009 document (removed in December 2009 ⚠️) — so yeah, these are giving limited-edition, archive-only, don't-count-on-them energy:

  • SB_FORWARD.ANY — (Event 02H, Umask 01H) counts the number of store forwards 💫.
  • LOAD_BLOCK.STD — (Event 03H, Umask 01H) counts the loads blocked by a preceding store with unknown data.
  • LOAD_BLOCK.ADDRESS_OFFSET — (Event 03H, Umask 04H) counts the loads blocked by a preceding store address.
  • LOAD_BLOCK.ADDRESS_OFFSET — (Event 01H, Umask 04H) counts the cycles of store buffer drains 😮‍💨. (yes bestie, same name as the one above, different event — that's genuinely what the doc says, not me glitching)
  • MISALIGN_MEM_REF.LOAD — (Event 05H, Umask 01H) counts the number of misaligned load references.
  • MISALIGN_MEM_REF.STORE — (Event 05H, Umask 02H) counts the number of misaligned store references.
  • MISALIGN_MEM_REF.ANY — (Event 05H, Umask 03H) counts the number of misaligned memory references.
  • STORE_BLOCKS.NOT_STA — (Event 06H, Umask 01H) counts the load operations delayed by preceding stores whose addresses are known but whose data is unknown, plus preceding stores that conflict with the load but only incompletely overlap it 🫠.
  • STORE_BLOCKS.STA — (Event 06H, Umask 02H) counts load operations delayed by preceding stores whose addresses are unknown (STA block).
  • STORE_BLOCKS.ANY — (Event 06H, Umask 0FH) all loads delayed due to store blocks 💀.
  • MEMORY_DISAMBIGURATION.RESET — (Event 09H, Umask 01H) counts memory disambiguration reset cycles.
  • MEMORY_DISAMBIGURATION.SUCCESS — (Event 09H, Umask 02H) counts the loads where memory disambiguration succeeded ✅.
  • MEMORY_DISAMBIGURATION.WATCHDOG — (Event 09H, Umask 04H) counts how many times the memory disambiguration watchdog kicked in 🐕.
  • MEMORY_DISAMBIGURATION.WATCH_CYCLES — (Event 09H, Umask 08H) counts the cycles the memory disambiguration watchdog is active. set invert=1, cmask = 1.
  • HW_INT.RCV — (Event 1DH, Umask 01H) number of interrupts received.
  • HW_INT.CYCLES_MASKED — (Event 1DH, Umask 02H) number of cycles interrupts are masked 🙈.
  • HW_INT.CYCLES_PENDING_AND_MASKED — (Event 1DH, Umask 04H) number of cycles interrupts are pending and masked.
  • HW_INT.CYCLES_PENDING_AND_MASKED — (Event 04H, Umask 04H) counts L2 store RFO requests where the cache line to be loaded is in the E (exclusive) state. The L1D prefetcher does not issue a RFO prefetch — this is a demand RFO request 💅. (same name again, different event code, we love a reused label)
  • HW_INT.CYCLES_PENDING_AND_MASKED — (Event 27H, Umask 04H) LONGEST_LAT_CACH E.MISS (copying this one exactly as it's written, spaces and all — not my typo to fix 🔍)
  • UOPS_DECODED.DEC0 — (Event 3DH, Umask 01H) counts micro-ops decoded by decoder 0 ⭐.
  • UOPS_DECODED.DEC0 — (Event 01H, Umask 01H) counts L1 data cache store RFO requests where the cache line to be loaded is in the I state. Counter 0, 1 only (and yes, same name, different event — the doc said it twice and so did I)
  • 0FH — (Event 41H, Umask 41H) L1D_CACHE_ST.MESI counts L1 data cache store RFO requests. Counter 0, 1 only. (genuinely the whole name is 0FH, I'm not messing with you 🍓)
  • DTLB_MISSES.PDE_MISS — (Event 49H, Umask 20H) number of DTLB cache misses where the low part of the linear to physical address translation was missed.
  • DTLB_MISSES.PDP_MISS — (Event 49H, Umask 40H) number of DTLB misses where the high part of the linear to physical address translation was missed.
  • DTLB_MISSES.LARGE_WALK_COMPLETED — (Event 49H, Umask 80H) counts the completed large page walks due to misses in the STLB 🚶‍♀️.
  • SSE_MEM_EXEC.NTA — (Event 4BH, Umask 01H) counts SSE NTA prefetch / weakly-ordered instructions that missed the L1 data cache.
  • SSE_MEM_EXEC.STREAMING_STORES — (Event 4BH, Umask 08H) counts the number of SSE non temporal stores 🌊.
  • SFENCE_CYCLES — (Event 4DH, Umask 01H) counts store fence cycles 🚧.
  • EPT.EPDE_MISS — (Event 4FH, Umask 02H) counts Extended Page Directory Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches 🖥️✨.

continuing the event list, bestie — every single one is here, no cap:

  • EPT.EPDPE_HIT — Event 4FH, Umask 04H. Counts Extended Page Directory Pointer Entry hits. ✨
  • EPT.EPDPE_MISS — Event 4FH, Umask 08H. Counts Extended Page Directory Pointer Entry misses. 💅
  • OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA — Event 60H, Umask 01H. Counts weighted cycles of offcore demand data read requests. Does not include L2 prefetch requests. counter 0. 🫶
  • OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE — Event 60H, Umask 02H. Counts weighted cycles of offcore demand code read requests. Does not include L2 prefetch requests. counter 0. 🫶
  • OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO — Event 60H, Umask 04H. Counts weighted cycles of offcore demand RFO requests. Does not include L2 prefetch requests. counter 0. 🫶
  • OFFCORE_REQUESTS_OUTSTANDING.ANY.READ — Event 60H, Umask 08H. Counts weighted cycles of offcore read requests of any kind. Includes L2 prefetch requests. counter 0. 🫶
  • IFU_IVC.FULL — Event 81H, Umask 01H. The Instruction Fetch unit victim cache is full. 😭
  • IFU_IVC.L1I_EVICTION — Event 81H, Umask 02H. L1 Instruction cache evictions. 🌸
  • L1I_OPPORTUNISTIC_HITS — Event 83H, Umask 01H. Opportunistic hits in streaming. ⭐
  • ITLB_MISSES.WALK_CYCLES — Event 85H, Umask 04H. Counts ITLB miss page walk cycles. 🦋
  • ITLB_MISSES.PMH_BUSY_CYCLES — Event 85H, Umask 04H. Counts PMH busy cycles. 🦋
  • ITLB_MISSES.STLB_HIT — Event 85H, Umask 10H. Counts the number of ITLB misses that hit in the second level TLB. 💜
  • ITLB_MISSES.PDE_MISS — Event 85H, Umask 20H. Number of ITLB misses where the low part of the linear to physical address translation was missed. 🔥
  • ITLB_MISSES.PDP_MISS — Event 85H, Umask 40H. Number of ITLB misses where the high part of the linear to physical address translation was missed. 🔥
  • ITLB_MISSES.LARGE_WALK_COMPLETED — Event 85H, Umask 80H. Counts the number of completed large page walks due to misses in the STLB. 👑
  • ITLB_MISSES.LARGE_WALK_COMPLETED — Event 01H, Umask 80H. Counts the number of offcore demand data read requests. Does not count L2 prefetch requests. Yes bestie, the same name shows up twice with different event/umask numbers — both stay. 🙈
  • OFFCORE_REQUESTS.DEMAND.READ_CODE — Event B0H, Umask 02H. Counts the number of offcore demand code read requests. Does not count L2 prefetch requests. 💖
  • OFFCORE_REQUESTS.DEMAND.RFO — Event B0H, Umask 04H. Counts the number of offcore demand RFO requests. Does not count L2 prefetch requests. 💖
  • OFFCORE_REQUESTS.ANY.READ — Event B0H, Umask 08H. Counts the number of offcore read requests. Includes L2 prefetch requests. 🌈
  • OFFCORE_REQUESTS.ANY.RFO — Event B0H, Umask 10H. Counts the number of offcore RFO requests. Includes L2 prefetch requests. 🌈
  • OFFCORE_REQUESTS.UNCACHED_MEM — Event B0H, Umask 20H. Counts the number of offcore uncached memory requests. 🧚
  • OFFCORE_REQUESTS.ANY — Event B0H, Umask 80H. Counts all offcore requests. 💫
  • SNOOPQ_REQUESTS_OUTSTANDING.DATA — Event B3H, Umask 01H. Counts weighted cycles of snoopq requests for data. Counter 0 only; use cmask=1 to count cycles that are not empty. 🫶
  • SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE — Event B3H, Umask 02H. Counts weighted cycles of snoopq invalidate requests. Counter 0 only; use cmask=1 to count cycles that are not empty. 🫶
  • SNOOPQ_REQUESTS_OUTSTANDING.CODE — Event B3H, Umask 04H. Counts weighted cycles of snoopq requests for code. Counter 0 only; use cmask=1 to count cycles that are not empty. 🫶
  • SNOOPQ_REQUESTS_OUTSTANDING.CODE — Event BAH, Umask 04H. Counts the number of TPR reads. Another same-name moment, different numbers — iconic duplicate energy, both listed. 🎀
  • PIC_ACCESSES.TPR_WRITES — Event BAH, Umask 02H. Counts the number of TPR writes that are one or two micro-ops. Some instructions are decoded into longer sequences. 🌸
  • MACHINE_CLEARS.FUSION_ASSIST — Event C3H, Umask 10H. Counts the number of macro-fusion assists. Also counts retired SIMD packed single- precision floating point Uops. 🔥
  • BOGUS_BR — Event E4H, Umask 01H. Counts the number of bogus branches. 💀
  • L2_HW_PREFETCH.HIT — Event F3H, Umask 01H. Counts L2 HW prefetcher detector hits. ✨
  • L2_HW_PREFETCH.ALLOC — Event F3H, Umask 02H. Counts L2 HW prefetcher allocations. ✨
  • L2_HW_PREFETCH.DATA_TRIGGER — Event F3H, Umask 04H. Counts L2 HW data prefetcher triggered. 🦋
  • L2_HW_PREFETCH.CODE_TRIGGER — Event F3H, Umask 08H. Counts L2 HW code prefetcher triggered. 🦋
  • L2_HW_PREFETCH.DCA_TRIGGER — Event F3H, Umask 10H. Counts L2 HW DCA prefetcher triggered. 🦋
  • L2_HW_PREFETCH.KICK_START — Event F3H, Umask 20H. Counts L2 HW prefetcher kick started. ⭐
  • SQ_MISC.PROMOTION — Event F4H, Umask 01H. Counts the number of L2 secondary misses that hit the Super Queue. 👑
  • SQ_MISC.PROMOTION_POST_GO — Event F4H, Umask 02H. Counts the number of L2 secondary misses during the Super Queue filling L2. 👑
  • SQ_MISC.LRU_HINTS — Event F4H, Umask 04H. Counts the number of Super Queue LRU hints sent to L3. 💜
  • SQ_MISC.FILL_DROPPED — Event F4H, Umask 08H. Counts the number of SQ L2 fills dropped due to L2 busy. 😭
  • SEGMENT_REG_LOADS — Event F8H, Umask 01H. Counts the number of segment register loads. 🎀

🌈 SEE ALSO 🌈

💜 HISTORY 💜

The pmc library first appeared in FreeBSD 6.0. ⭐

👑 AUTHORS 👑

The Performance Counters Library (libpmc, -lpmc) library was written by Joseph Koshy <jkoshy@FreeBSD.org>. 💖

okay that’s the end of the page — footer vibe check: Debian, March 24, 2010, PMC.COREI7(3). iconic. 🎀

📦 where this page comes from
  • freebsd 15.1: base 15.1
  • Copyright (c) 2010 Fabien Thomas. All rights reserved
  • 💖 girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms