PMC.IVYBRIDGEXEON(3)

💅 PMC.IVYBRIDGEXEON — measurement events for Intel Ivy Bridge Xeon family CPUs

Okay bestie, so this is a manual page from section 3 — PMC.IVYBRIDGEXEON(3), like, the whole title. Let's get into it 🦋

✨ NAME ✨

pmc.ivybridgexeon — measurement events for Intel Ivy Bridge Xeon family CPUs. That's the vibe: it's the page that tells you which perf counters you can poke on these specific chips 💖

📚 LIBRARY 📚

Performance Counters Library (libpmc, -lpmc). Yeah, you link with -lpmc, that's the whole thing 🎀

🧚 SYNOPSIS 🧚

#include <pmc.h>

That's it. That's the include. Iconic.

🌸 DESCRIPTION 🌸

So, Intel Ivy Bridge Xeon CPUs contain PMCs conforming to version 2 of the Intel performance measurement architecture. No cap, they're fancy like that.

These CPUs may contain up to three classes of PMCs:

• PMC_CLASS_IAF — fixed-function counters that count only one hardware event per counter. One job, one counter, she's committed 💅
• PMC_CLASS_IAP — programmable counters that may be configured to count one of a defined set of hardware events. Pick your fighter ✨

The number of PMCs available in each class and their widths need to be determined at run time by calling pmc_cpuinfo(3). So like, don't hardcode it, bestie, ask nicely at runtime 🙈

Intel Ivy Bridge Xeon PMCs are documented in Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Order Number: 325462-045US, Intel Corporation, January 2013. (Yes, that's the citation, copy it into your notes, periodt.)

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🎀 IVYBRIDGE FIXED FUNCTION PMCS 🎀

These PMCs and their supported events are documented in pmc.iaf(3). Go read that one for the fixed-function deets 🫶

🔥 IVYBRIDGE PROGRAMMABLE PMCS 🔥

The programmable PMCs support the following capabilities — biggest flex table ever, but as bullets because we're cute like that:

• PMC_CAP_CASCADE — No
• PMC_CAP_EDGE — Yes
• PMC_CAP_INTERRUPT — Yes
• PMC_CAP_INVERT — Yes
• PMC_CAP_READ — Yes
• PMC_CAP_PRECISE — No
• PMC_CAP_SYSTEM — Yes
• PMC_CAP_TAGGING — No
• PMC_CAP_THRESHOLD — Yes
• PMC_CAP_USER — Yes
• PMC_CAP_WRITE — Yes

💜 Event Qualifiers 💜

Event specifiers for these PMCs support the following common qualifiers:

• rsp=value — Configure the Off-core Response bits. And ooh girl, there are so many of these, buckle up:
  • REQ_DMND_DATA_RD — Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches.
  • REQ_DMND_RFO — Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches.
  • REQ_DMND_IFETCH — Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches.
  • REQ_WB — Counts the number of writeback (modified to exclusive) transactions.
  • REQ_PF_DATA_RD — Counts the number of data cacheline reads generated by L2 prefetchers.
  • REQ_PF_RFO — Counts the number of RFO requests generated by L2 prefetchers.
  • REQ_PF_IFETCH — Counts the number of code reads generated by L2 prefetchers.
  • REQ_PF_LLC_DATA_RD — L2 prefetcher to L3 for loads.
  • REQ_PF_LLC_RFO — RFO requests generated by L2 prefetcher.
  • REQ_PF_LLC_IFETCH — L2 prefetcher to L3 for instruction fetches.
  • REQ_BUS_LOCKS — Bus lock and split lock requests.
  • REQ_STRM_ST — Streaming store requests.
  • REQ_OTHER — Any other request that crosses IDI, including I/O.
  • RES_ANY — Catch all value for any response types.
  • RES_SUPPLIER_NO_SUPP — No Supplier Information available.
  • RES_SUPPLIER_LLC_HITM — M-state initial lookup stat in L3.
  • RES_SUPPLIER_LLC_HITE — E-state.
  • RES_SUPPLIER_LLC_HITS — S-state.
  • RES_SUPPLIER_LLC_HITF — F-state.
  • RES_SUPPLIER_LOCAL — Local DRAM Controller.
  • RES_SNOOP_SNP_NONE — No details on snoop-related information.
  • RES_SNOOP_SNP_NO_NEEDED — No snoop was needed to satisfy the request.
  • RES_SNOOP_SNP_MISS — A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM.
  • RES_SNOOP_HIT_NO_FWD — A snoop was needed and it hits in at least one snooped cache. Hit denotes a cache-line was valid before snoop effect. This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM.
  • RES_SNOOP_HIT_FWD — A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
  • RES_SNOOP_HITM — A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a cache-line was in modified state before effect as a results of snoop. This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD).
  • RES_NON_DRAM — Target was non-DRAM system address. This includes MMIO transactions.
• cmask=value — Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to value.
• edge — Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. (One and done, she doesn't double-count 😌)
• inv — Invert the sense of comparison when the "cmask" qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the "cmask" qualifier.
• os — Configure the PMC to count events happening at processor privilege level 0.
• usr — Configure the PMC to count events occurring at privilege levels 1, 2 or 3.

💡 If neither of the "os" or "usr" qualifiers are specified, the default is to enable both. So like, you get everything unless you specifically gate it ✨

⭐ Event Specifiers (Programmable PMCs) ⭐

Ivy Bridge programmable PMCs support the following events — this is the long part bestie, but we're getting through all of them fr fr:

• LD_BLOCKS.STORE_FORWARD — (Event 03H, Umask 02H) loads blocked by overlapping with store buffer that cannot be forwarded .
• MISALIGN_MEM_REF.LOADS — (Event 05H, Umask 01H) Speculative cache-line split load uops dispatched to L1D.
• MISALIGN_MEM_REF.STORES — (Event 05H, Umask 02H) Speculative cache-line split Store-address uops dispatched to L1D.
• LD_BLOCKS_PARTIAL.ADDRESS_ALIAS — (Event 07H, Umask 01H) False dependencies in MOB due to partial compare on address.
• DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK — (Event 08H, Umask 81H) Misses in all TLB levels that cause a page walk of any page size from demand loads.
• DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED — (Event 08H, Umask 82H) Misses in all TLB levels that caused page walk completed of any size by demand loads.
• DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION — (Event 08H, Umask 84H) Cycle PMH is busy with a walk due to demand loads.
• UOPS_ISSUED.ANY — (Event 0EH, Umask 01H) Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1to count stalled cycles. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.
• UOPS_ISSUED.FLAGS_MERGE — (Event 0EH, Umask 10H) Number of flags-merge uops allocated. Such uops adds delay.
• UOPS_ISSUED.SLOW_LEA — (Event 0EH, Umask 20H) Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.
• UOPS_ISSUED.SINGLE_MUL — (Event 0EH, Umask 40H) Number of multiply packed/scalar single precision uops allocated.
• ARITH.FPU_DIV_ACTIVE — (Event 14H, Umask 01H) Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.
• L2_RQSTS.DEMAND_DATA_RD_HIT — (Event 24H, Umask 01H) Demand Data Read requests that hit L2 cache.
• L2_RQSTS.ALL_DEMAND_DATA_RD — (Event 24H, Umask 03H) Counts any demand and L1 HW prefetch data load requests to L2.
• L2_RQSTS.RFO_HITS — (Event 24H, Umask 04H) Counts the number of store RFO requests that hit the L2 cache.
• L2_RQSTS.RFO_MISS — (Event 24H, Umask 08H) Counts the number of store RFO requests that miss the L2 cache.
• L2_RQSTS.ALL_RFO — (Event 24H, Umask 0CH) Counts all L2 store RFO requests.
• L2_RQSTS.CODE_RD_HIT — (Event 24H, Umask 10H) Number of instruction fetches that hit the L2 cache.
• L2_RQSTS.CODE_RD_MISS — (Event 24H, Umask 20H) Number of instruction fetches that missed the L2 cache.
• L2_RQSTS.ALL_CODE_RD — (Event 24H, Umask 30H) Counts all L2 code requests.
• L2_RQSTS.PF_HIT — (Event 24H, Umask 40H) Counts all L2 HW prefetcher requests that hit L2.
• L2_RQSTS.PF_MISS — (Event 24H, Umask 80H) Counts all L2 HW prefetcher requests that missed L2.
• L2_RQSTS.ALL_PF — (Event 24H, Umask C0H) Counts all L2 HW prefetcher requests.
• L2_STORE_LOCK_RQSTS.MISS — (Event 27H, Umask 01H) RFOs that miss cache lines.
• L2_STORE_LOCK_RQSTS.HIT_M — (Event 27H, Umask 08H) RFOs that hit cache lines in M state.
• L2_STORE_LOCK_RQSTS.ALL — (Event 27H, Umask 0FH) RFOs that access cache lines in any state.
• L2_L1D_WB_RQSTS.MISS — (Event 28H, Umask 01H) Not rejected writebacks that missed LLC.
• L2_L1D_WB_RQSTS.HIT_E — (Event 28H, Umask 04H) Not rejected writebacks from L1D to L2 cache lines in E state.
• L2_L1D_WB_RQSTS.HIT_M — (Event 28H, Umask 08H) Not rejected writebacks from L1D to L2 cache lines in M state.
• L2_L1D_WB_RQSTS.ALL — (Event 28H, Umask 0FH) Not rejected writebacks from L1D to L2 cache lines in any state.

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Ok we're not done yet — there's more of this page coming, so don't go anywhere bestie 🌈

LONGEST_LAT_CACHE.REFERENCE

(Event 2EH, Umask 4FH) — counts the requests coming from the core that reference a cache line in the last level cache 💖 literally the core looking at LLC and going "hey, you".

LONGEST_LAT_CACHE.MISS

(Event 2EH, Umask 41H) — counts every single cache miss condition for references to the last level cache 😭 oof, the LLC said no.

CPU_CLK_UNHALTED.THREAD_P

(Event 3CH, Umask 00H) — counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it's running the HLT instruction 🛌. Heads up bestie: the core frequency may change from time to time due to power or thermal throttling — so this is counting cycles, not seconds, periodt.

CPU_CLK_THREAD_UNHALTED.REF_XCLK

(Event 3CH, Umask 01H) — increments at the frequency of XCLK (100 MHz) while not halted ⏰.

L1D_PEND_MISS.PENDING

(Event 48H, Umask 01H) — increments the number of outstanding L1D misses every cycle. Set Cmaks = 1 and Edge =1 to count occurrences. Counter 2 only. Set Cmask = 1 to count cycles 👀 (yes it really says Cmaks in the source, we don't fix, we report).

DTLB_STORE_MISSES.MISS_CAUSES_A_WALK

(Event 49H, Umask 01H) — a miss in all TLB levels that causes a page walk of any page size (4K/2M/4M/1G) 🚶‍♀️.

DTLB_STORE_MISSES.WALK_COMPLETED

(Event 49H, Umask 02H) — a miss in all TLB levels that causes a page walk that completes, of any page size (4K/2M/4M/1G) ✨ she finished the walk, we love a finisher.

DTLB_STORE_MISSES.WALK_DURATION

(Event 49H, Umask 04H) — cycles PMH is busy with this walk 💅 busy busy.

DTLB_STORE_MISSES.STLB_HIT

(Event 49H, Umask 10H) — store operations that miss the first TLB level but hit the second and do not cause page walks 🎯 close enough, no walk needed.

LOAD_HIT_PRE.SW_PF

(Event 4CH, Umask 01H) — non-SW-prefetch load dispatches that hit a fill buffer allocated for S/W prefetch 🌸.

LOAD_HIT_PRE.HW_PF

(Event 4CH, Umask 02H) — non-SW-prefetch load dispatches that hit a fill buffer allocated for H/W prefetch 🦋.

L1D.REPLACEMENT

(Event 51H, Umask 01H) — counts the number of lines brought into the L1 data cache 🎀 new lines moving in, so iconic.

MOVE_ELIMINATION.INT_NOT_ELIMINATED

(Event 58H, Umask 01H) — number of integer Move Elimination candidate uops that were not eliminated 😔 the elimination did not eliminate, it's giving irony.

MOVE_ELIMINATION.SIMD_NOT_ELIMINATED

(Event 58H, Umask 02H) — number of SIMD Move Elimination candidate uops that were not eliminated 🙈.

MOVE_ELIMINATION.INT_ELIMINATED

(Event 58H, Umask 04H) — number of integer Move Elimination candidate uops that were eliminated 👑 slay, gone, never seen again.

MOVE_ELIMINATION.SIMD_ELIMINATED

(Event 58H, Umask 08H) — number of SIMD Move Elimination candidate uops that were eliminated 🔥.

CPL_CYCLES.RING0

(Event 5CH, Umask 01H) — unhalted core cycles when the thread is in ring 0 👑 kernel mode main character energy. Use Edge to count transition.

CPL_CYCLES.RING123

(Event 5CH, Umask 02H) — unhalted core cycles when the thread is not in ring 0 🌈 userspace era.

RS_EVENTS.EMPTY_CYCLES

(Event 5EH, Umask 01H) — cycles the RS is empty for the thread 🫥 nothing in the reservation station, ghost town.

DTLB_LOAD_MISSES.STLB_HIT

(Event 5FH, Umask 04H) — counts load operations that missed 1st level DTLB but hit the 2nd level 💜 second time's the charm.

OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD

(Event 60H, Umask 01H) — offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles 🍓.

OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD

(Event 60H, Umask 02H) — offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles 🧚.

OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO

(Event 60H, Umask 04H) — offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles 💫.

OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD

(Event 60H, Umask 08H) — offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles ⭐.

LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION

(Event 63H, Umask 01H) — cycles in which the L1D and L2 are locked, due to a UC lock or split lock 🔒 both levels locked, it's giving chaos.

LOCK_CYCLES.CACHE_LOCK_DURATION

(Event 63H, Umask 02H) — cycles in which the L1D is locked 🔐 just the one level this time.

IDQ.EMPTY

(Event 79H, Umask 02H) — counts cycles the IDQ is empty 💀 nothing to do, the queue is on break.

IDQ.MITE_UOPS

(Event 79H, Umask 04H) — increment each cycle # of uops delivered to IDQ from the MITE path. Can combine Umask 04H and 20H. Set Cmask = 1 to count cycles ✨.

IDQ.DSB_UOPS

(Event 79H, Umask 08H) — increment each cycle # of uops delivered to IDQ from the DSB path. Can combine Umask 08H and 10H. Set Cmask = 1 to count cycles 🦋.

IDQ.MS_DSB_UOPS

(Event 79H, Umask 10H) — increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery. Can combine Umask 04H, 08H 🎀.

IDQ.MS_MITE_UOPS

(Event 79H, Umask 20H) — increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H 🌸.

IDQ.MS_UOPS

(Event 79H, Umask 30H) — increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H 🌈.

IDQ.ALL_DSB_CYCLES_ANY_UOPS

(Event 79H, Umask 18H) — counts cycles DSB is delivered at least one uops. Set Cmask = 1 💅.

IDQ.ALL_DSB_CYCLES_4_UOPS

(Event 79H, Umask 18H) — counts cycles DSB is delivered four uops. Set Cmask = 4 🍓.

IDQ.ALL_MITE_CYCLES_ANY_UOPS

(Event 79H, Umask 24H) — counts cycles MITE is delivered at least one uops. Set Cmask = 1 🔥.

IDQ.ALL_MITE_CYCLES_4_UOPS

(Event 79H, Umask 24H) — counts cycles MITE is delivered four uops. Set Cmask = 4 👑.

IDQ.MITE_ALL_UOPS

(Event 79H, Umask 3CH) — # of uops delivered to IDQ from any path 🛣️ all roads lead to IDQ.

ICACHE.MISSES

(Event 80H, Umask 02H) — number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses 😭 it's a whole trio of misses bestie.

ITLB_MISSES.MISS_CAUSES_A_WALK

(Event 85H, Umask 01H) — misses in all ITLB levels that cause page walks 🚶.

ITLB_MISSES.WALK_COMPLETED

(Event 85H, Umask 02H) — misses in all ITLB levels that cause completed page walks ✅.

ITLB_MISSES.WALK_DURATION

(Event 85H, Umask 04H) — cycle PMH is busy with a walk ⏳.

ITLB_MISSES.STLB_HIT

(Event 85H, Umask 10H) — number of cache load STLB hits. No page walk 🎉 we love to see it.

ILD_STALL.LCP

(Event 87H, Umask 01H) — stalls caused by changing prefix length of the instruction 😵‍💫 the prefix changed and everything stopped.

ILD_STALL.IQ_FULL

(Event 87H, Umask 04H) — stall cycles due to IQ is full 🈵 no room, no vibes.

BR_INST_EXEC.NONTAKEN_COND

(Event 88H, Umask 41H) — counts conditional near branch instructions that were executed (but not necessarily retired) and not taken 🙅‍♀️.

BR_INST_EXEC.TAKEN_COND

(Event 88H, Umask 81H) — counts conditional near branch instructions that were executed (but not necessarily retired) and taken ✅.

BR_INST_EXEC.DIRECT_JMP

(Event 88H, Umask 82H) — counts all unconditional near branch instructions excluding calls and indirect branches 🦘.

BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET

(Event 88H, Umask 84H) — counts executed indirect near branch instructions that are not calls nor returns 🌀.

BR_INST_EXEC.RETURN_NEAR

(Event 88H, Umask 88H) — counts indirect near branches that have a return mnemonic 🏠 coming back home.

BR_INST_EXEC.DIRECT_NEAR_CALL

(Event 88H, Umask 90H) — counts unconditional near call branch instructions, excluding non call branch, executed 📞.

BR_INST_EXEC.INDIRECT_NEAR_CALL

(Event 88H, Umask A0H) — counts indirect near calls, including both register and memory indirect, executed 📲.

BR_INST_EXEC.ALL_BRANCHES

(Event 88H, Umask FFH) — counts all near executed branches (not necessarily retired) 🌈 the whole gang.

BR_MISP_EXEC.NONTAKEN_COND

(Event 89H, Umask 41H) — counts conditional near branch instructions mispredicted as nontaken 😬 the predictor guessed wrong.

BR_MISP_EXEC.TAKEN_COND

(Event 89H, Umask 81H) — counts conditional near branch instructions mispredicted as taken 🙈 also wrong, different direction.

BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET

(Event 89H, Umask 84H) — counts mispredicted indirect near branch instructions that are not calls nor returns 💀.

BR_MISP_EXEC.RETURN_NEAR

(Event 89H, Umask 88H) — counts mispredicted indirect near branches that have a return mnemonic 😭 the return got predicted wrong, embarrassing.

BR_MISP_EXEC.DIRECT_NEAR_CALL

(Event 89H, Umask 90H) — counts mispredicted unconditional near call branch instructions, excluding non call branch, executed 🫠.

BR_MISP_EXEC.INDIRECT_NEAR_CALL

(Event 89H, Umask A0H) — counts mispredicted indirect near calls, including both register and memory indirect, executed 🤡.

BR_MISP_EXEC.ALL_BRANCHES

(Event 89H, Umask FFH) — counts all mispredicted near executed branches (not necessarily retired) 🔥 every wrong guess in one number, iconic.

IDQ_UOPS_NOT_DELIVERED.CORE

(Event 9CH, Umask 01H) — counts number of non-delivered uops to RAT per thread. Use Cmask to qualify uop b/w 🎯.

UOPS_DISPATCHED_PORT.PORT_0

(Event A1H, Umask 01H) — cycles which a Uop is dispatched on port 0 🛤️.

UOPS_DISPATCHED_PORT.PORT_1

(Event A1H, Umask 02H) — cycles which a Uop is dispatched on port 1 🛤️.

UOPS_DISPATCHED_PORT.PORT_2_LD

(Event A1H, Umask 04H) — cycles which a load uop is dispatched on port 2 📥.

UOPS_DISPATCHED_PORT.PORT_2_STA

(Event A1H, Umask 08H) — cycles which a store address uop is dispatched on port 2 📤.

UOPS_DISPATCHED_PORT.PORT_2

(Event A1H, Umask 0CH) — cycles which a Uop is dispatched on port 2 🛤️ the whole port, no filter.

UOPS_DISPATCHED_PORT.PORT_3_LD

(Event A1H, Umask 10H) — cycles which a load uop is dispatched on port 3 📥.

UOPS_DISPATCHED_PORT.PORT_3_STA

(Event A1H, Umask 20H) — cycles which a store address uop is dispatched on port 3 📤.

UOPS_DISPATCHED_PORT.PORT_3

(Event A1H, Umask 30H) — cycles which a Uop is dispatched on port 3 🛤️.

UOPS_DISPATCHED_PORT.PORT_4

(Event A1H, Umask 40H) — cycles which a Uop is dispatched on port 4 🛤️.

UOPS_DISPATCHED_PORT.PORT_5

(Event A1H, Umask 80H) — cycles which a Uop is dispatched on port 5 🛤️.

RESOURCE_STALLS.ANY

(Event A2H, Umask 01H) — cycles Allocation is stalled due to a Resource Related reason 🚧 anything resource-y counts here.

RESOURCE_STALLS.RS

(Event A2H, Umask 04H) — cycles stalled due to no eligible RS entry available 😔 the RS had nothing for you bestie.

• RESOURCE_STALLS.SB — Event A2H, Umask 08H — cycles stalled because there were literally no store buffers available (and no, that does not include draining form sync) 😭
• RESOURCE_STALLS.ROB — Event A2H, Umask 08H... wait no bestie, it's Umask 10H — cycles stalled because the re-order buffer was full 🫠
• CYCLE_ACTIVITY.CYCLES_L2_PENDING — Event A3H, Umask 01H — cycles with pending L2 miss loads. Set AnyThread to count per core ⭐
• CYCLE_ACTIVITY.CYCLES_LDM_PENDING — Event A3H, Umask 02H — cycles with pending memory loads. Also set AnyThread to count per core 💅
• CYCLE_ACTIVITY.CYCLES_NO_EXECUTE — Event A3H, Umask 04H — cycles of dispatch stalls. Again: AnyThread for per-core counting 🎀
• CYCLE_ACTIVITY.CYCLES_L1D_PENDING — Event A3H, Umask 08H — cycles with pending L1 cache miss loads. You already know the drill: AnyThread = per core ✨
• DSB2MITE_SWITCHES.COUNT — Event ABH, Umask 01H — how many DSB to MITE switches happened 🔁
• DSB2MITE_SWITCHES.PENALTY_CYCLES — Event ABH, Umask 02H — cycles of delay caused by those DSB to MITE switches 💀
• DSB_FILL.EXCEED_DSB_LINES — Event ACH, Umask 08H — a DSB Fill that ran into more than 3 DSB lines 🦋
• ITLB.ITLB_FLUSH — Event AEH, Umask 01H — counts ITLB flushes, and yes it includes 4k/2M/4M pages 🧚
• OFFCORE_REQUESTS.DEMAND_DATA_RD — Event B0H, Umask 01H — demand data read requests that got sent to uncore 📨
• OFFCORE_REQUESTS.DEMAND_CODE_RD — Event B0H, Umask 02H — demand code read requests sent to uncore 📬
• OFFCORE_REQUESTS.DEMAND_RFO — Event B0H, Umask 04H — demand RFO read requests sent to uncore, and it includes regular RFOs, locks, and ItoM 🔥
• OFFCORE_REQUESTS.ALL_DATA_RD — Event B0H, Umask 08H — data read requests sent to uncore, both demand and prefetch 👑
• UOPS_EXECUTED.THREAD — Event B1H, Umask 01H — counts the total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV = 1 to count stall cycles 🫶
• UOPS_EXECUTED.CORE — Event B1H, Umask 02H — counts the total number of uops to be executed per-core each cycle. Good news: you do not need to set ANY 🙈
• OFF_CORE_RESPONSE_0 — Event B7H, Umask 01H — Off-core Response Performance Monitoring. PMC0 only, and it requires programming MSR 01A6H ⚠️
• OFF_CORE_RESPONSE_1 — Event BBH, Umask 01H — Off-core Response Performance Monitoring. PMC3 only, and this one requires programming MSR 01A7H ⚠️
• TLB_FLUSH.DTLB_THREAD — Event BDH, Umask 01H — DTLB flush attempts of the thread-specific entries 🌸
• TLB_FLUSH.STLB_ANY — Event BDH, Umask 20H — counts the number of STLB flush attempts 🌀
• INST_RETIRED.ANY_P — Event C0H, Umask 00H — number of instructions at retirement 🎓
• INST_RETIRED.ALL — Event C0H, Umask 01H — a precise instruction retired event with HW to reduce the effect of PEBS shadow in IP distribution. PMC1 only, and you must quiesce other PMCs 💀
• OTHER_ASSISTS.AVX_STORE — Event C1H, Umask 08H — number of assists tied to 256-bit AVX store operations 💾
• OTHER_ASSISTS.AVX_TO_SSE — Event C1H, Umask 10H — number of transitions from AVX-256 to legacy SSE when the penalty applies 😬
• OTHER_ASSISTS.SSE_TO_AVX — Event C1H, Umask 20H — number of transitions from SSE to AVX-256 when the penalty applies 😬
• UOPS_RETIRED.ALL — Event C2H, Umask 01H — counts the number of micro-ops retired. Use cmask=1 and invert to count active cycles or stalled cycles. Supports PEBS, and use Any=1 for core granularity ⭐
• UOPS_RETIRED.RETIRE_SLOTS — Event C2H, Umask 02H — counts the number of retirement slots used each cycle 🎰
• MACHINE_CLEARS.MEMORY_ORDERING — Event C3H, Umask 02H — counts the number of machine clears due to memory order conflicts 🧠
• MACHINE_CLEARS.SMC — Event C3H, Umask 04H — number of self-modifying-code machine clears detected 🪄
• MACHINE_CLEARS.MASKMOV — Event C3H, Umask 20H — counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0 🚨
• BR_INST_RETIRED.ALL_BRANCHES — Event C4H, Umask 00H — branch instructions at retirement 🌿
• BR_INST_RETIRED.CONDITIONAL — Event C4H, Umask 01H — counts the number of conditional branch instructions retired. Supports PEBS ✅
• BR_INST_RETIRED.NEAR_CALL — Event C4H, Umask 02H — direct and indirect near call instructions retired 📞
• BR_INST_RETIRED.ALL_BRANCHES — Event C4H, Umask 04H — counts the number of branch instructions retired (yes, same name, different umask — that's not a typo, that's the vibe) 🌈
• BR_INST_RETIRED.NEAR_RETURN — Event C4H, Umask 08H — counts the number of near return instructions retired ↩️
• BR_INST_RETIRED.NOT_TAKEN — Event C4H, Umask 10H — counts the number of not taken branch instructions retired 🙅
• BR_INST_RETIRED.NEAR_TAKEN — Event C4H, Umask 20H — number of near taken branches retired 🏃
• BR_INST_RETIRED.FAR_BRANCH — Event C4H, Umask 40H — number of far branches retired 🛫
• BR_MISP_RETIRED.ALL_BRANCHES — Event C5H, Umask 00H — mispredicted branch instructions at retirement 💀
• BR_MISP_RETIRED.CONDITIONAL — Event C5H, Umask 01H — mispredicted conditional branch instructions retired. Supports PEBS ✅
• BR_MISP_RETIRED.NEAR_CALL — Event C5H, Umask 02H — direct and indirect mispredicted near call instructions retired 📞💥
• BR_MISP_RETIRED.ALL_BRANCHES — Event C5H, Umask 04H — mispredicted macro branch instructions retired 🧵
• BR_MISP_RETIRED.NOT_TAKEN — Event C5H, Umask 10H — mispredicted not taken branch instructions retired 🙅💀
• BR_MISP_RETIRED.TAKEN — Event C5H, Umask 20H — mispredicted taken branch instructions retired 🏃💀
• FP_ASSIST.X87_OUTPUT — Event CAH, Umask 02H — number of X87 FP assists due to Output values 🔢
• FP_ASSIST.X87_INPUT — Event CAH, Umask 04H — number of X87 FP assists due to input values 🔣
• FP_ASSIST.SIMD_OUTPUT — Event CAH, Umask 08H — number of SIMD FP assists due to Output values 💫
• FP_ASSIST.SIMD_INPUT — Event CAH, Umask 10H — number of SIMD FP assists due to input values 🌟
• FP_ASSIST.ANY — Event CAH, Umask 1EH — cycles with any input/output SSE* or FP assists ✨
• ROB_MISC_EVENTS.LBR_INSERTS — Event CCH, Umask 20H — counts the cases of saving new LBR records by hardware 📼
• MEM_TRANS_RETIRED.LOAD_LATENCY — Event CDH, Umask 01H — sample loads with a specified latency threshold. PMC3 only, and you specify the threshold in MSR 0x3F6 ⏱️
• MEM_TRANS_RETIRED.PRECISE_STORE — Event CDH, Umask 02H — sample stores and collect precise store operation via PEBS record. PMC3 only 📦
• MEM_UOPS_RETIRED.STLB_MISS_LOADS — Event D0H, Umask 11H — count retired load uops that missed the STLB 😵
• MEM_UOPS_RETIRED.STLB_MISS_STORES — Event D0H, Umask 12H — count retired store uops that missed the STLB 😵
• MEM_UOPS_RETIRED.SPLIT_LOADS — Event D0H, Umask 41H — count retired load uops that got split across a cache line ✂️
• MEM_UOPS_RETIRED.SPLIT_STORES — Event D0H, Umask 42H — count retired store uops that got split across a cache line ✂️
• MEM_UOPS_RETIRED.ALL_LOADS — Event D0H, Umask 81H — count all retired load uops 📥
• MEM_UOPS_RETIRED.ALL_STORES — Event D0H, Umask 82H — count all retired store uops 📤
• MEM_LOAD_UOPS_RETIRED.L1_HIT — Event D1H, Umask 01H — retired load uops with L1 cache hits as data sources. Supports PEBS ✅
• MEM_LOAD_UOPS_RETIRED.L2_HIT — Event D1H, Umask 02H — retired load uops with L2 cache hits as data sources 🎯
• MEM_LOAD_UOPS_RETIRED.LLC_HIT — Event D1H, Umask 04H — retired load uops whose data source was an LLC hit with no snoop required 💅
• MEM_LOAD_UOPS_RETIRED.LLC_MISS — Event D1H, Umask 20H — retired load uops whose data source is an LLC miss 😭
• MEM_LOAD_UOPS_RETIRED.HIT_LFB — Event D1H, Umask 40H — retired load uops whose data sources were load uops that missed L1 but hit FB due to a preceding miss to the same cache line with data not ready 🧩
• MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS — Event D2H, Umask 01H — retired load uops whose data sources were LLC hit and cross-core snoop missed in on-pkg core cache. Supports PEBS ✅
• MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT — Event D2H, Umask 02H — retired load uops whose data sources were LLC and cross-core snoop hits in on-pkg core cache. Supports PEBS ✅
• MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM — Event D2H, Umask 04H — retired load uops whose data sources were HitM responses from shared LLC 🤝
• MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE — Event D2H, Umask 08H — retired load uops whose data sources were hits in LLC without snoops required 🎀
• MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM — Event D3H, Umask 01H — retired load uops whose data sources missed LLC but were serviced from local dram. Supports PEBS ✅
• MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM — Event D3H, Umask 04H — retired load uops whose data source was remote DRAM 🌐
• MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM — Event D3H, Umask 10H — retired load uops whose data source was remote HITM 📡
• MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD — Event D3H, Umask 20H — retired load uops whose data source was forwards from a remote cache 🔀
• BACLEARS.ANY — Event E6H, Umask 1FH — number of front end re-steers due to BPU misprediction 🎢
• L2_TRANS.DEMAND_DATA_RD — Event F0H, Umask 01H — Demand Data Read requests that access L2 cache 📊
• L2_TRANS.RFO — Event F0H, Umask 02H — RFO requests that access L2 cache 🔒
• L2_TRANS.CODE_RD — Event F0H, Umask 04H — L2 cache accesses when fetching instructions 📜
• L2_TRANS.ALL_PF — Event F0H, Umask 08H — any MLC or LLC HW prefetch accessing L2, including rejects 🚫
• L2_TRANS.L1D_WB — Event F0H, Umask 10H — L1D writebacks that access L2 cache 💦
• L2_TRANS.L2_FILL — Event F0H, Umask 20H — L2 fill requests that access L2 cache 🧃
• L2_TRANS.L2_WB — Event F0H, Umask 40H — L2 writebacks that access L2 cache 🚰
• L2_TRANS.ALL_REQUESTS — Event F0H, Umask 80H — transactions accessing L2 pipe 🛣️
• L2_LINES_IN.I — Event F1H, Umask 01H — L2 cache lines in I state filling L2. Heads up: counting does not cover rejects 🙅♀️

okay bestie that's a whole lot of counters but we're not even done yet — keep scrolling, there's more 👑

• L2_LINES_IN.S — (Event F1H, Umask 02H) L2 cache lines in S state filling L2. Counting does not cover rejects. ✨
• L2_LINES_IN.E — (Event F1H, Umask 04H) L2 cache lines in E state filling L2. Counting does not cover rejects. 💫
• L2_LINES_IN.ALL — (Event F1H, Umask 07H) L2 cache lines filling L2. Counting does not cover rejects. 👑
• L2_LINES_OUT.DEMAND_CLEAN — (Event F2H, Umask 01H) Clean L2 cache lines evicted by demand. 🧹
• L2_LINES_OUT.DEMAND_DIRTY — (Event F2H, Umask 02H) Dirty L2 cache lines evicted by demand. 🙈
• L2_LINES_OUT.PF_CLEAN — (Event F2H, Umask 04H) Clean L2 cache lines evicted by the MLC prefetcher. 🦋
• L2_LINES_OUT.PF_DIRTY — (Event F2H, Umask 08H) Dirty L2 cache lines evicted by the MLC prefetcher. 💅
• L2_LINES_OUT.DIRTY_ALL — (Event F2H, Umask 0AH) Dirty L2 cache lines filling the L2. 🔥

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🌈 SEE ALSO 🌈

okay bestie, here's the whole squad, all of them linked and none of them skipped 💖

pmc(3), pmc.amd(3), pmc.atom(3), pmc.core(3), pmc.corei7(3), pmc.corei7uc(3), pmc.iaf(3), pmc.ivybridge(3), pmc.sandybridge(3), pmc.sandybridgeuc(3), pmc.sandybridgexeon(3), pmc.soft(3), pmc.tsc(3), pmc.ucf(3), pmc.westmere(3), pmc.westmereuc(3), pmc_cpuinfo(3), pmclog(3), hwpmc(4)

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🎀 HISTORY 🎀

The pmc library first appeared in FreeBSD 6.0. like, it's been iconic since day one, no cap 🫶

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💜 AUTHORS 💜

The Performance Counters Library (libpmc, -lpmc) library was written by Joseph Koshy <jkoshy@FreeBSD.org>. 💫

The support for the Ivy Bridge Xeon microarchitecture was written by Hiren Panchasara <hiren.panchasara@gmail.com>. 🌸

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and that's a wrap on PMC.IVYBRIDGEXEON(3) bestie, go count some cache lines and slay 💅✨

Debian · January 25, 2013 · PMC.IVYBRIDGEXEON(3) 🦋