PMC.HASWELL(3)

okay so welcome to PMC.HASWELL(3), bestie 💖 this is a Library Functions Manual page, and it's the whole tea on Intel Haswell measurement events. grab a snack, we're getting into it 🍓

✨ NAME ✨

pmc.haswell — measurement events for Intel Haswell family CPUs 🎀

🌸 LIBRARY 🌸

Performance Counters Library (libpmc, -lpmc) — literally just link it, iykyk 💅

🦋 SYNOPSIS 🦋

#include <pmc.h>

that's it. that's the whole synopsis. iconic.

👑 DESCRIPTION 👑

okay so Intel Haswell CPUs contain PMCs that conform to version 2 of the Intel performance measurement architecture. these CPUs may contain up to two classes of PMCs:

• PMC_CLASS_IAF — fixed-function counters that count only one hardware event per counter.
• PMC_CLASS_IAP — programmable counters that may be configured to count one of a defined set of hardware events.

the number of PMCs available in each class and their widths? you do not get to guess that, bestie — you have to determine it at run time by calling pmc_cpuinfo(3) 🫶

Intel Haswell PMCs are documented in “Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C”, Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Order Number: 325462-045US, Intel Corporation, January 2013. very "here's my source, I cited it" of them 📚

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⭐ HASWELL FIXED FUNCTION PMCS ⭐

these PMCs and their supported events are documented in pmc.iaf(3). go read that one, it's a whole separate vibe.

🔥 HASWELL PROGRAMMABLE PMCS 🔥

the programmable PMCs support the following capabilities:

• PMC_CAP_CASCADE — No 🙈
• PMC_CAP_EDGE — Yes ✨
• PMC_CAP_INTERRUPT — Yes ✨
• PMC_CAP_INVERT — Yes ✨
• PMC_CAP_READ — Yes ✨
• PMC_CAP_PRECISE — No 💀
• PMC_CAP_SYSTEM — Yes ✨
• PMC_CAP_TAGGING — No 💀
• PMC_CAP_THRESHOLD — Yes ✨
• PMC_CAP_USER — Yes ✨
• PMC_CAP_WRITE — Yes ✨

like, mostly yes, but PMC_CAP_CASCADE, PMC_CAP_PRECISE and PMC_CAP_TAGGING are a hard no on this chip. noted. moving on 🌈

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🎀 Event Qualifiers 🎀

event specifiers for these PMCs support the following common qualifiers:

• rsp=value — configure the Off-core Response bits. and inside that there's a whole menu, so buckle up:
  • DMND_DATA_RD — counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. does not count L2 data read prefetches or instruction fetches.
  • REQ_DMND_RFO — counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. does not count L2 RFO prefetches.
  • REQ_DMND_IFETCH — counts the number of demand and DCU prefetch instruction cacheline reads. does not count L2 code read prefetches.
  • REQ_WB — counts the number of writeback (modified to exclusive) transactions.
  • REQ_PF_DATA_RD — counts the number of data cacheline reads generated by L2 prefetchers.
  • REQ_PF_RFO — counts the number of RFO requests generated by L2 prefetchers.
  • REQ_PF_IFETCH — counts the number of code reads generated by L2 prefetchers.
  • REQ_PF_LLC_DATA_RD — L2 prefetcher to L3 for loads.
  • REQ_PF_LLC_RFO — RFO requests generated by L2 prefetcher
  • REQ_PF_LLC_IFETCH — L2 prefetcher to L3 for instruction fetches.
  • REQ_BUS_LOCKS — bus lock and split lock requests.
  • REQ_STRM_ST — streaming store requests.
  • REQ_OTHER — any other request that crosses IDI, including I/O.
  • RES_ANY — catch all value for any response types.
  • RES_SUPPLIER_NO_SUPP — no Supplier Information available.
  • RES_SUPPLIER_LLC_HITM — M-state initial lookup stat in L3.
  • RES_SUPPLIER_LLC_HITE — E-state.
  • RES_SUPPLIER_LLC_HITS — S-state.
  • RES_SUPPLIER_LLC_HITF — F-state.
  • RES_SUPPLIER_LOCAL — local DRAM Controller.
  • RES_SNOOP_SNP_NONE — no details on snoop-related information.
  • RES_SNOOP_SNP_NO_NEEDED — no snoop was needed to satisfy the request.
  • RES_SNOOP_SNP_MISS — a snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM.
  • RES_SNOOP_HIT_NO_FWD — a snoop was needed and it hits in at least one snooped cache. Hit denotes a cache-line was valid before snoop effect. this includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S). In the LLC Miss case, data is returned from DRAM.
  • RES_SNOOP_HIT_FWD — a snoop was needed and data was forwarded from a remote socket. this includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
  • RES_SNOOP_HITM — a snoop was needed and it HitM-ed in local or remote cache. HitM denotes a cache-line was in modified state before effect as a results of snoop. this includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD).
  • RES_NON_DRAM — target was non-DRAM system address. this includes MMIO transactions.
• cmask=value — configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to value.
• edge — configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. if specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true.
• inv — invert the sense of comparison when the <pink>cmask</pink> qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the <pink>cmask</pink> qualifier.
• os — configure the PMC to count events happening at processor privilege level 0.
• usr — configure the PMC to count events occurring at privilege levels 1, 2 or 3.

🫶 if neither of the <pink>os</pink> or <pink>usr</pink> qualifiers are specified, the default is to enable both. so like, you get both unless you say otherwise. generous of them, tbh.

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💜 Event Specifiers (Programmable PMCs) 💜

Haswell programmable PMCs support the following events — and yes, we're doing all of them, no skipping 💅

• LD_BLOCKS.STORE_FORWARD — (Event 03H, Umask 02H) Loads blocked by overlapping with store buffer that cannot be forwarded.
• MISALIGN_MEM_REF.LOADS — (Event 05H, Umask 01H) Speculative cache-line split load uops dispatched to L1D.
• MISALIGN_MEM_REF.STORES — (Event 05H, Umask 02H) Speculative cache-line split Store-address uops dispatched to L1D.
• LD_BLOCKS_PARTIAL.ADDRESS_ALIAS — (Event 07H, Umask 01H) False dependencies in MOB due to partial compare on address.
• DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK — (Event 08H, Umask 01H) Misses in all TLB levels that cause a page walk of any page size.
• DTLB_LOAD_MISSES.WALK_COMPLETED_4K — (Event 08H, Umask 02H) Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.
• DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K — (Event 08H, Umask 02H) Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.
• DTLB_LOAD_MISSES.WALK_COMPLETED — (Event 08H, Umask 0EH) Completed page walks in any TLB of any page size due to demand load misses
• DTLB_LOAD_MISSES.WALK_DURATION — (Event 08H, Umask 10H) Cycle PMH is busy with a walk.
• DTLB_LOAD_MISSES.STLB_HIT_4K — (Event 08H, Umask 20H) Load misses that missed DTLB but hit STLB (4K).
• DTLB_LOAD_MISSES.STLB_HIT_2M — (Event 08H, Umask 40H) Load misses that missed DTLB but hit STLB (2M).
• DTLB_LOAD_MISSES.STLB_HIT — (Event 08H, Umask 60H) Number of cache load STLB hits. No page walk.
• DTLB_LOAD_MISSES.PDE_CACHE_MISS — (Event 08H, Umask 80H) DTLB demand load misses with low part of linear-to- physical address translation missed
• INT_MISC.RECOVERY_CYCLES — (Event 0DH, Umask 03H) Cycles waiting to recover after Machine Clears except JEClear. Set Cmask = 1.
• UOPS_ISSUED.ANY — (Event 0EH, Umask 01H) increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any = 1 to count stalled cycles of this core.
• UOPS_ISSUED.FLAGS_MERGE — (Event 0EH, Umask 10H) Number of flags-merge uops allocated. Such uops adds delay.
• UOPS_ISSUED.SLOW_LEA — (Event 0EH, Umask 20H) Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.
• UOPS_ISSUED.SiNGLE_MUL — (Event 0EH, Umask 40H) Number of multiply packed/scalar single precision uops allocated. (and yes, that capital S in the middle is fr fr how it's written — don't @ me, I don't make the rules 💀)
• L2_RQSTS.DEMAND_DATA_RD_MISS — (Event 24H, Umask 21H) Demand Data Read requests that missed L2, no rejects.
• L2_RQSTS.DEMAND_DATA_RD_HIT — (Event 24H, Umask 41H) Demand Data Read requests that hit L2 cache.
• L2_RQSTS.ALL_DEMAND_DATA_RD — (Event 24H, Umask E1H) Counts any demand and L1 HW prefetch data load requests to L2.
• L2_RQSTS.RFO_HIT — (Event 24H, Umask 42H) Counts the number of store RFO requests that hit the L2 cache.
• L2_RQSTS.RFO_MISS — (Event 24H, Umask 22H) Counts the number of store RFO requests that miss the L2 cache.
• L2_RQSTS.ALL_RFO — (Event 24H, Umask E2H) Counts all L2 store RFO requests.
• L2_RQSTS.CODE_RD_HIT — (Event 24H, Umask 44H) Number of instruction fetches that hit the L2 cache.
• L2_RQSTS.CODE_RD_MISS — (Event 24H, Umask 24H) Number of instruction fetches that missed the L2 cache.
• L2_RQSTS.ALL_DEMAND_MISS — (Event 24H, Umask 27H) Demand requests that miss L2 cache.
• L2_RQSTS.ALL_DEMAND_REFERENCES — (Event 24H, Umask E7H) Demand requests to L2 cache.
• L2_RQSTS.ALL_CODE_RD — (Event 24H, Umask E4H) Counts all L2 code requests.
• L2_RQSTS.L2_PF_HIT — (Event 24H, Umask 50H) Counts all L2 HW prefetcher requests that hit L2.

and that's where part one taps out — the L2_RQSTS saga does not end here, so stay tuned bestie 🦋💖

ok still rolling through the event list, bestie — grab a snack, there's a lot of TLB lore coming 💅

• L2_RQSTS.L2_PF_MISS (Event 24H, Umask 30H) — counts, like, every single L2 HW prefetcher request that missed L2. all of them. the whole vibe.
• L2_RQSTS.ALL_PF (Event 24H, Umask F8H) — counts all L2 HW prefetcher requests, periodt.
• L2_RQSTS.MISS (Event 24H, Umask 3FH) — every request that missed L2. that's it. that's the event.
• L2_RQSTS.REFERENCES (Event 24H, Umask FFH) — all requests to L2 cache, the whole population ✨
• L2_DEMAND_RQSTS.WB_HIT (Event 27H, Umask 50H) — writebacks that hit L2 cache and were not rejected. we love a hit that stays hit 🫶
• LONGEST_LAT_CACHE.REFERENCE (Event 2EH, Umask 4FH) — counts requests coming from the core that reference a cache line in the last level cache.
• LONGEST_LAT_CACHE.MISS (Event 2EH, Umask 41H) — counts each cache miss condition for references to the last level cache. the sad path 😭
• CPU_CLK_UNHALTED.THREAD_P (Event 3CH, Umask 00H) — counts the number of thread cycles while the thread is not in a halt state. the thread enters halt when it's running the HLT instruction. also heads up: the core frequency may change from time to time due to power or thermal throttling 🔥 — so yeah, that's a thing.
• CPU_CLK_THREAD_UNHALTED.REF_XCLK (Event 3CH, Umask 01H) — increments at the frequency of XCLK (100 MHz) when not halted.
• L1D_PEND_MISS.PENDING (Event 48H, Umask 01H) — increments the number of outstanding L1D misses every cycle. set Cmaks = 1 and Edge =1 to count occurrences. (yes, Cmaks. keeping it exactly as written, iykyk 🙈)
• DTLB_STORE_MISSES.MISS_CAUSES_A_WALK (Event 49H, Umask 01H) — a miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G).
• DTLB_STORE_MISSES.WALK_COMPLETED_4K (Event 49H, Umask 02H) — completed page walks due to store misses in one or more TLB levels of 4K page structure.
• DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M (Event 49H, Umask 04H) — completed page walks due to store misses in one or more TLB levels of 2M/4M page structure. big pages, big energy 🌸
• DTLB_STORE_MISSES.WALK_COMPLETED (Event 49H, Umask 0EH) — completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G). the inclusive queen 👑
• DTLB_STORE_MISSES.WALK_DURATION (Event 49H, Umask 10H) — cycles PMH is busy with this walk.
• DTLB_STORE_MISSES.STLB_HIT_4K (Event 49H, Umask 20H) — store misses that missed DTLB but hit STLB (4K). missed the first one, caught the second, iconic 💅
• DTLB_STORE_MISSES.STLB_HIT_2M (Event 49H, Umask 40H) — store misses that missed DTLB but hit STLB (2M).
• DTLB_STORE_MISSES.STLB_HIT (Event 49H, Umask 60H) — store operations that miss the first TLB level but hit the second and do not cause page walks. no walk, no stress 🧚
• DTLB_STORE_MISSES.PDE_CACHE_MISS (Event 49H, Umask 80H) — DTLB store misses with low part of linear-to-physical address translation missed.
• LOAD_HIT_PRE.SW_PF (Event 4CH, Umask 01H) — non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.
• LOAD_HIT_PRE.HW_PF (Event 4CH, Umask 02H) — non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.
• L1D.REPLACEMENT (Event 51H, Umask 01H) — counts the number of lines brought into the L1 data cache.
• MOVE_ELIMINATION.INT_NOT_ELIMINATED (Event 58H, Umask 04H) — number of integer Move Elimination candidate uops that were not eliminated. they didn't make the cut 😔
• MOVE_ELIMINATION.SMID_NOT_ELIMINATED (Event 58H, Umask 08H) — number of SIMD Move Elimination candidate uops that were not eliminated.
• MOVE_ELIMINATION.INT_ELIMINATED (Event 58H, Umask 01H) — unhalted core cycles when the thread is in ring 0.
• MOVE_ELIMINATION.SMID_ELIMINATED (Event 58H, Umask 02H) — number of SIMD Move Elimination candidate uops that were eliminated. slay, eliminated 💀
• CPL_CYCLES.RING0 (Event 5CH, Umask 02H) — unhalted core cycles when the thread is in ring 0. kernel mode main character energy.
• CPL_CYCLES.RING123 (Event 5CH, Umask 01H) — unhalted core cycles when the thread is not in ring 0.
• RS_EVENTS.EMPTY_CYCLES (Event 5EH, Umask 01H) — cycles the RS is empty for the thread. empty. nothing. void. 🕳️
• OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD (Event 60H, Umask 01H) — offcore outstanding Demand Data Read transactions in SQ to uncore. set Cmask=1 to count cycles.
• OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD (Event 60H, Umask 02H) — offcore outstanding Demand code Read transactions in SQ to uncore. set Cmask=1 to count cycles.
• OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO (Event 60H, Umask 04H) — offcore outstanding RFO store transactions in SQ to uncore. set Cmask=1 to count cycles.
• OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD (Event 60H, Umask 08H) — offcore outstanding cacheable data read transactions in SQ to uncore. set Cmask=1 to count cycles.
• LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION (Event 63H, Umask 01H) — cycles in which the L1D and L2 are locked, due to a UC lock or split lock. both caches, held hostage 🔒
• LOCK_CYCLES.CACHE_LOCK_DURATION (Event 63H, Umask 02H) — cycles in which the L1D is locked.
• IDQ.EMPTY (Event 79H, Umask 02H) — counts cycles the IDQ is empty.
• IDQ.MITE_UOPS (Event 79H, Umask 04H) — increment each cycle # of uops delivered to IDQ from MITE path. set Cmask = 1 to count cycles.
• IDQ.DSB_UOPS (Event 79H, Umask 08H) — increment each cycle. # of uops delivered to IDQ from DSB path. set Cmask = 1 to count cycles.
• IDQ.MS_DSB_UOPS (Event 79H, Umask 10H) — increment each cycle # of uops delivered to IDQ when MS_busy by DSB. set Cmask = 1 to count cycles. add Edge=1 to count # of delivery.
• IDQ.MS_MITE_UOPS (Event 79H, Umask 20H) — ncrement each cycle # of uops delivered to IDQ when MS_busy by MITE. set Cmask = 1 to count cycles. (that's ncrement, no i — she's quirky like that, don't come for her 🙈)
• IDQ.MS_UOPS (Event 79H, Umask 30H) — increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. set Cmask = 1 to count cycles.
• IDQ.ALL_DSB_CYCLES_ANY_UOPS (Event 79H, Umask 18H) — counts cycles DSB is delivered at least one uops. set Cmask = 1.
• IDQ.ALL_DSB_CYCLES_4_UOPS (Event 79H, Umask 18H) — counts cycles DSB is delivered four uops. set Cmask=4.
• IDQ.ALL_MITE_CYCLES_ANY_UOPS (Event 79H, Umask 24H) — counts cycles MITE is delivered at least one uops. set Cmask = 1.
• IDQ.ALL_MITE_CYCLES_4_UOPS (Event 79H, Umask 24H) — counts cycles MITE is delivered four uops. set Cmask =4.
• IDQ.MITE_ALL_UOPS (Event 79H, Umask 3CH) — # of uops delivered to IDQ from any path. any. all. the works 🌀
• ICACHE.MISSES (Event 80H, Umask 02H) — number of Instruction Cache, Streaming Buffer and Victim Cache Misses. includes UC accesses.
• ITLB_MISSES.MISS_CAUSES_A_WALK (Event 85H, Umask 01H) — misses in ITLB that causes a page walk of any page size.
• ITLB_MISSES.WALK_COMPLETED_4K (Event 85H, Umask 02H) — completed page walks due to misses in ITLB 4K page entries.
• TLB_MISSES.WALK_COMPLETED_2M_4M (Event 85H, Umask 04H) — completed page walks due to misses in ITLB 2M/4M page entries. (yes the event name says TLB_MISSES up top, not ITLB_MISSES — writing it exactly as she is, no notes 💅)
• ITLB_MISSES.WALK_COMPLETED (Event 85H, Umask 0EH) — completed page walks in ITLB of any page size.
• ITLB_MISSES.WALK_DURATION (Event 85H, Umask 10H) — cycle PMH is busy with a walk.
• ITLB_MISSES.STLB_HIT_4K (Event 85H, Umask 20H) — ITLB misses that hit STLB (4K).
• ITLB_MISSES.STLB_HIT_2M (Event 85H, Umask 40H) — ITLB misses that hit STLB (2K). (the page says 2K and i'm not gonna gaslight you about it 🫶)
• ITLB_MISSES.STLB_HIT (Event 85H, Umask 60H) — TLB misses that hit STLB. no page walk.
• ILD_STALL.LCP (Event 87H, Umask 01H) — stalls caused by changing prefix length of the instruction.
• ILD_STALL.IQ_FULL (Event 87H, Umask 04H) — stall cycles due to IQ is full.
• BR_INST_EXEC.NONTAKEN_COND (Event 88H, Umask 41H) — counts conditional near branch instructions that were executed (but not necessarily retired) and not taken.
• BR_INST_EXEC.TAKEN_COND (Event 88H, Umask 81H) — counts conditional near branch instructions that were executed (but not necessarily retired) and taken. she took the branch, she's braver than me 😭
• BR_INST_EXEC.DIRECT_JMP (Event 88H, Umask 82H) — counts all unconditional near branch instructions excluding calls and indirect branches.
• BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET (Event 88H, Umask 84H) — counts executed indirect near branch instructions that are not calls nor returns.
• BR_INST_EXEC.RETURN_NEAR (Event 88H, Umask 88H) — counts indirect near branches that have a return mnemonic.
• BR_INST_EXEC.DIRECT_NEAR_CALL (Event 88H, Umask 90H) — counts unconditional near call branch instructions, excluding non call branch, executed.
• BR_INST_EXEC.INDIRECT_NEAR_CALL (Event 88H, Umask A0H) — counts indirect near calls, including both register and memory indirect, executed.
• BR_INST_EXEC.ALL_BRANCHES (Event 88H, Umask FFH) — counts all near executed branches (not necessarily retired). the full collection ✨
• BR_MISP_EXEC.NONTAKEN_COND (Event 89H, Umask 41H) — counts conditional near branch instructions mispredicted as nontaken.
• BR_MISP_EXEC.TAKEN_COND (Event 89H, Umask 81H) — counts conditional near branch instructions mispredicted as taken.
• BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET (Event 89H, Umask 84H) — counts mispredicted indirect near branch instructions that are not calls nor returns.
• BR_MISP_EXEC.RETURN_NEAR (Event 89H, Umask 88H) — counts mispredicted indirect near branches that have a return mnemonic.
• BR_MISP_EXEC.DIRECT_NEAR_CALL (Event 89H, Umask 90H) — counts mispredicted unconditional near call branch instructions, excluding non call branch, executed.
• BR_MISP_EXEC.INDIRECT_NEAR_CALL (Event 89H, Umask A0H) — counts mispredicted indirect near calls, including both register and memory indirect, executed.
• BR_MISP_EXEC.ALL_BRANCHES (Event 89H, Umask FFH) — counts all mispredicted near executed branches (not necessarily retired). the misprediction hall of shame 💀
• IDQ_UOPS_NOT_DELIVERED.CORE (Event 9CH, Umask 01H) — count number of non-delivered uops to RAT per thread.
• UOPS_EXECUTED_PORT.PORT_0 (Event A1H, Umask 01H) — cycles which a Uop is dispatched on port 0 in this thread.
• UOPS_EXECUTED_PORT.PORT_1 (Event A1H, Umask 02H) — cycles which a Uop is dispatched on port 1 in this thread.

still going bestie, don't close the tab yet 🦋

• UOPS_EXECUTED_PORT.PORT_2 — (Event A1H, Umask 04H) cycles where a uop gets dispatched on port 2 in this thread ✨
• UOPS_EXECUTED_PORT.PORT_3 — (Event A1H, Umask 08H) cycles where a uop gets dispatched on port 3 in this thread
• UOPS_EXECUTED_PORT.PORT_4 — (Event A1H, Umask 10H) cycles where a uop gets dispatched on port 4 in this thread
• UOPS_EXECUTED_PORT.PORT_5 — (Event A1H, Umask 20H) cycles where a uop gets dispatched on port 5 in this thread
• UOPS_EXECUTED_PORT.PORT_6 — (Event A1H, Umask 40H) cycles where a uop gets dispatched on port 6 in this thread
• UOPS_EXECUTED_PORT.PORT_7 — (Event A1H, Umask 80H) cycles where a uop gets dispatched on port 7 in this thread

💅 ok ports 0 and 1 were in the last chunk, these are the rest of the squad, we love a complete set.

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• RESOURCE_STALLS.ANY — (Event A2H, Umask 01H) cycles where allocation is stalled for a resource-related reason 😭
• RESOURCE_STALLS.RS — (Event A2H, Umask 04H) cycles stalled because there's no eligible RS entry available
• RESOURCE_STALLS.SB — (Event A2H, Umask 08H) cycles stalled because no store buffers are available (and nope, that does not include draining form sync)
• RESOURCE_STALLS.ROB — (Event A2H, Umask 10H) cycles stalled because the re-order buffer is full 🫠
• CYCLE_ACTIVITY.CYCLES_L2_PENDING — (Event A3H, Umask 01H) cycles with pending L2 miss loads. Set Cmask=2 to count cycle 👑
• CYCLE_ACTIVITY.CYCLES_LDM_PENDING — (Event A3H, Umask 02H) cycles with pending memory loads. Set Cmask=2 to count cycle
• CYCLE_ACTIVITY.STALLS_L2_PENDING — (Event A3H, Umask 05H) number of loads that missed L2
• CYCLE_ACTIVITY.CYCLES_L1D_PENDING — (Event A3H, Umask 08H) cycles with pending L1 cache miss loads. Set Cmask=8 to count cycle ⭐

bestie pls note the Cmask values are literally part of the vibe check here — 2, 2, and 8 respectively. don't come for me, that's what the page says 💖

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• ITLB.ITLB_FLUSH — (Event AEH, Umask 01H) counts the number of ITLB flushes, and yes it includes 4k/2M/4M pages 🦋
• OFFCORE_REQUESTS.DEMAND_DATA_RD — (Event B0H, Umask 01H) demand data read requests sent to uncore
• OFFCORE_REQUESTS.DEMAND_CODE_RD — (Event B0H, Umask 02H) demand code read requests sent to uncore
• OFFCORE_REQUESTS.DEMAND_RFO — (Event B0H, Umask 04H) demand RFO read requests sent to uncore, including regular RFOs, locks, and ItoM
• OFFCORE_REQUESTS.ALL_DATA_RD — (Event B0H, Umask 08H) data read requests sent to uncore — both demand and prefetch, we're counting everybody 🎀
• UOPS_EXECUTED.CORE — (Event B1H, Umask 02H) counts the total number of uops to be executed per-core each cycle
• OFF_CORE_RESPONSE_0 — (Event B7H, Umask 01H) requires MSR 01A6H 🔥
• OFF_CORE_RESPONSE_1 — (Event BBH, Umask 01H) requires MSR 01A7H

ngl these two are giving "special guest star" energy — they literally need an MSR to even exist. main character events only 💅

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• PAGE_WALKER_LOADS.DTLB_L1 — (Event BCH, Umask 11H) number of DTLB page walker loads that hit in the L1+FB
• PAGE_WALKER_LOADS.ITLB_L1 — (Event BCH, Umask 21H) number of ITLB page walker loads that hit in the L1+FB
• PAGE_WALKER_LOADS.DTLB_L2 — (Event BCH, Umask 12H) number of DTLB page walker loads that hit in the L2
• PAGE_WALKER_LOADS.ITLB_L2 — (Event BCH, Umask 22H) number of ITLB page walker loads that hit in the L2
• PAGE_WALKER_LOADS.DTLB_L3 — (Event BCH, Umask 14H) number of DTLB page walker loads that hit in the L3
• PAGE_WALKER_LOADS.ITLB_L3 — (Event BCH, Umask 24H) number of ITLB page walker loads that hit in the L3
• PAGE_WALKER_LOADS.DTLB_MEMORY — (Event BCH, Umask 18H) number of DTLB page walker loads from memory 💀
• PAGE_WALKER_LOADS.ITLB_MEMORY — (Event BCH, Umask 28H) number of ITLB page walker loads from memory

lowkey obsessed with how these are all Event BCH with different umasks — it's giving one event, eight personalities 🌈

• TLB_FLUSH.DTLB_THREAD — (Event BDH, Umask 01H) DTLB flush attempts of the thread-specific entries
• TLB_FLUSH.STLB_ANY — (Event BDH, Umask 20H) count the number of STLB flush attempts

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• INST_RETIRED.ANY_P — (Event C0H, Umask 00H) number of instructions at retirement 👑
• INST_RETIRED.ALL — (Event C0H, Umask 01H) precise instruction retired event with HW to reduce the effect of PEBS shadow in IP distribution ✨
• OTHER_ASSISTS.AVX_TO_SSE — (Event C1H, Umask 08H) number of transitions from AVX-256 to legacy SSE when penalty is applicable
• OTHER_ASSISTS.SSE_TO_AVX — (Event C1H, Umask 10H) number of transitions from SSE to AVX-256 when penalty is applicable
• OTHER_ASSISTS.ANY_WB_ASSIST — (Event C1H, Umask 40H) number of microcode assists invoked by HW upon uop writeback 🧚
• UOPS_RETIRED.ALL — (Event C2H, Umask 01H) counts the number of micro-ops retired. Use cmask=1 and invert to count active cycles or stalled cycles 🫶
• UOPS_RETIRED.RETIRE_SLOTS — (Event C2H, Umask 02H) counts the number of retirement slots used each cycle
• MACHINE_CLEARS.MEMORY_ORDERING — (Event C3H, Umask 02H) counts the number of machine clears due to memory order conflicts
• MACHINE_CLEARS.SMC — (Event C3H, Umask 04H) number of self-modifying-code machine clears detected 🙈
• MACHINE_CLEARS.MASKMOV — (Event C3H, Umask 20H) counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0

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• BR_INST_RETIRED.ALL_BRANCHES — (Event C4H, Umask 00H) branch instructions at retirement
• BR_INST_RETIRED.CONDITIONAL — (Event C4H, Umask 01H) counts the number of conditional branch instructions. Supports PEBS retired 🎀
• BR_INST_RETIRED.NEAR_CALL — (Event C4H, Umask 02H) direct and indirect near call instructions retired
• BR_INST_RETIRED.ALL_BRANCHES — (Event C4H, Umask 04H) counts the number of branch instructions retired

okay so yes, ALL_BRANCHES shows up twice with two different umasks (00H and 04H). Not me merging them — the page really does list both, so both stay. periodt 💅

• BR_INST_RETIRED.NEAR_RETURN — (Event C4H, Umask 08H) counts the number of near return instructions retired
• BR_INST_RETIRED.NOT_TAKEN — (Event C4H, Umask 10H) counts the number of not taken branch instructions retired
• BR_INST_RETIRED.NEAR_TAKEN — (Event C4H, Umask 20H) number of near taken branches retired

ngl the source page gets a lil glitchy right here — there's a stray It Li wedged into the text — but the deets are exactly as above: NOT_TAKEN is umask 10H, NEAR_TAKEN is umask 20H, both Event C4H 🦋

• BR_INST_RETIRED.FAR_BRANCH — (Event C4H, Umask 40H) number of far branches retired
• BR_MISP_RETIRED.ALL_BRANCHES — (Event C5H, Umask 00H) mispredicted branch instructions at retirement 😭
• BR_MISP_RETIRED.CONDITIONAL — (Event C5H, Umask 01H) mispredicted conditional branch instructions retired
• BR_MISP_RETIRED.CONDITIONAL — (Event C5H, Umask 04H) mispredicted macro branch instructions retired

again — same event name, two umasks, two meanings (01H = conditional, 04H = macro). Both listed, no cap 🫠

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• FP_ASSIST.X87_OUTPUT — (Event CAH, Umask 02H) number of X87 FP assists due to Output values
• FP_ASSIST.X87_INPUT — (Event CAH, Umask 04H) number of X87 FP assists due to input values
• FP_ASSIST.SIMD_OUTPUT — (Event CAH, Umask 08H) number of SIMD FP assists due to Output values
• FP_ASSIST.SIMD_INPUT — (Event CAH, Umask 10H) number of SIMD FP assists due to input values
• FP_ASSIST.ANY — (Event CAH, Umask 1EH) cycles with any input/output SSE* or FP assists ⭐
• ROB_MISC_EVENTS.LBR_INSERTS — (Event CCH, Umask 20H) counts cases of saving new LBR records by hardware
• MEM_TRANS_RETIRED.LOAD_LATENCY — (Event CDH, Umask 01H) randomly sampled loads whose latency is above a user defined threshold. A small fraction of the overall loads are sampled due to randomization 🌸

bestie this one is literally a sampler — it's supposed to miss most loads, that's the randomization doing its thing, not a bug 💖

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• MEM_UOPS_RETIRED.STLB_MISS_LOADS — (Event D0H, Umask 11H) count retired load uops that missed the STLB
• MEM_UOPS_RETIRED.STLB_MISS_STORES — (Event D0H, Umask 12H) count retired store uops that missed the STLB
• MEM_UOPS_RETIRED.SPLIT_LOADS — (Event D0H, Umask 41H) count retired load uops that were split across a cache line 💀
• MEM_UOPS_RETIRED.SPLIT_STORES — (Event D0H, Umask 42H) count retired store uops that were split across a cache line
• MEM_UOPS_RETIRED.ALL_LOADS — (Event D0H, Umask 81H) count all retired load uops
• MEM_UOPS_RETIRED.ALL_STORES — (Event D0H, Umask 82H) count all retired store uops 🔥
• MEM_LOAD_UOPS_RETIRED.L1_HIT — (Event D1H, Umask 01H) retired load uops with L1 cache hits as data sources
• MEM_LOAD_UOPS_RETIRED.L2_HIT — (Event D1H, Umask 02H) retired load uops with L2 cache hits as data sources
• MEM_LOAD_UOPS_RETIRED.LLC_HIT — (Event D1H, Umask 04H) retired load uops with LLC cache hits as data sources
• MEM_LOAD_UOPS_RETIRED.L2_MISS — (Event D1H, Umask 10H) retired load uops missed L2. Unknown data source excluded 🙈
• MEM_LOAD_UOPS_RETIRED.HIT_LFB — (Event D1H, Umask 40H) retired load uops whose data sources were load uops that missed L1 but hit FB due to a preceding miss to the same cache line with data not ready

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• MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS — (Event D2H, Umask 01H) retired load uops whose data sources were an LLC hit and a cross-core snoop missed in on-pkg core cache
• MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT — (Event D2H, Umask 02H) retired load uops whose data sources were LLC and cross-core snoop hits in on-pkg core cache 🦋
• MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM — (Event D2H, Umask 04H) retired load uops whose data sources were HitM responses from shared LLC
• MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE — (Event D2H, Umask 08H) retired load uops whose data sources were hits in LLC without snoops required 👑
• MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM — (Event D3H, Umask 01H) retired load uops whose data sources missed LLC but were serviced from local dram 💅

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• BACLEARS.ANY — (Event E6H, Umask 1FH) number of front end re-steers due to BPU misprediction
• L2_TRANS.DEMAND_DATA_RD — (Event F0H, Umask 01H) Demand Data Read requests that access L2 cache
• L2_TRANS.RFO — (Event F0H, Umask 02H) RFO requests that access L2 cache
• L2_TRANS.CODE_RD — (Event F0H, Umask 04H) L2 cache accesses when fetching instructions
• L2_TRANS.ALL_PF — (Event F0H, Umask 08H) any MLC or LLC HW prefetch accessing L2, including rejects 🌈
• L2_TRANS.L1D_WB — (Event F0H, Umask 10H) L1D writebacks that access L2 cache
• L2_TRANS.L2_FILL — (Event F0H, Umask 20H) L2 fill requests that access L2 cache
• L2_TRANS.L2_WB — (Event F0H, Umask 40H) L2 writebacks that access L2 cache ⭐
• L2_TRANS.ALL_REQUESTS — (Event F0H, Umask 80H) every single transaction that touches the L2 pipe. all of them. no skipping 💅
• L2_LINES_IN.I — (Event F1H, Umask 01H) L2 cache lines filling L2 while they're sitting in the I state 🧊
• L2_LINES_IN.S — (Event F1H, Umask 02H) L2 cache lines filling L2 while they're in the S state ✨
• L2_LINES_IN.E — (Event F1H, Umask 04H) L2 cache lines filling L2 while they're in the E state 🔥
• L2_LINES_IN.ALL — (Event F1H, Umask 07H) literally all the L2 cache lines filling L2, every state, the whole squad 🫶
• L2_LINES_OUT.DEMAND_CLEAN — (Event F2H, Umask 05H) clean L2 cache lines getting evicted by demand, bye bestie 👋
• L2_LINES_OUT.DEMAND_DIRTY — (Event F2H, Umask 06H) dirty L2 cache lines getting evicted by demand — messy, but make it performance-counter messy 💀

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🌈 SEE ALSO 🌈

okay so this is the friend group, go say hi to all of them:

• pmc(3)
• pmc.amd(3)
• pmc.atom(3)
• pmc.core(3)
• pmc.corei7(3)
• pmc.corei7uc(3)
• pmc.haswelluc(3)
• pmc.iaf(3)
• pmc.ivybridge(3)
• pmc.ivybridgexeon(3)
• pmc.sandybridge(3)
• pmc.sandybridgeuc(3)
• pmc.sandybridgexeon(3)
• pmc.soft(3)
• pmc.tsc(3)
• pmc.ucf(3)
• pmc.westmere(3)
• pmc.westmereuc(3)
• pmc_cpuinfo(3)
• pmclog(3)
• hwpmc(4)

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🕰️ HISTORY 🕰️

the pmc library first appeared in FreeBSD 6.0. like, it's been iconic since day one, no cap 👑

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👑 AUTHORS 👑

The Performance Counters Library (libpmc, -lpmc) library was written by Joseph Koshy <jkoshy@FreeBSD.org>.

The support for the Haswell microarchitecture was written by Hiren Panchasara <hiren.panchasara@gmail.com>.

absolute legends, both of them 🫶✨

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and that's the whole page bestie!! this beauty came from the Debian crew, dated March 22, 2013, and its whole entire name is PMC.HASWELL(3) 🎀 go forth and count those counters 💖🦋