PMC.ATOM(3)

📦

version 15.1 · 2 versions

15.1 · freebsd 15.1 (latest)
14.5 · freebsd 14.5

🦋 pmc.atom — measurement events for Intel Atom family CPUs 🦋

okay so this is the pmc.atom page from the Library Functions Manual — it's all about measurement events for Intel Atom family CPUs, and bestie, we're gonna get through it together 💖

✨ LIBRARY ✨

Performance Counters Library (libpmc, -lpmc) — yeah, that's the one, go link it 🎀

✨ SYNOPSIS ✨

#include <pmc.h>

that's it. that's the whole include. iconic.

🌸 DESCRIPTION 🌸

okay so picture this: Intel Atom CPUs ship with PMCs (performance monitoring counters, keep up 💅) that conform to version 3 of the Intel performance measurement architecture. And these CPUs contain two classes of PMCs:

PMC_CLASS_IAF — fixed-function counters, and the way they work is they count only one hardware event per counter. one event, one counter, no choices, no drama 💀
PMC_CLASS_IAP — programmable counters, which are the flexible ones: you can configure them to count one of a defined set of hardware events. slay.

now, the number of PMCs available in each class and their widths? those are not a vibe you can just assume — you have to determine them at run time by calling pmc_cpuinfo(3). don't skip that step fr fr 🔥

Intel Atom PMCs are documented in “Volume 3: System Programming Guide”, IA-32 Intel(R) Architecture Software Developer's Manual, Order Number 253669-027US, Intel Corporation, July 2008. go read the source, it's giving primary source energy 👑

👑 ATOM FIXED FUNCTION PMCS 👑

These PMCs and their supported events are documented in pmc.iaf(3). that's it, that's the whole subsection, go look there 🫶

💜 ATOM PROGRAMMABLE PMCS 💜

the programmable PMCs support the following capabilities, and I'm gonna list every single one because we don't skip:

PMC_CAP_CASCADE — No 🙈
PMC_CAP_EDGE — Yes ✨
PMC_CAP_INTERRUPT — Yes ✨
PMC_CAP_INVERT — Yes ✨
PMC_CAP_READ — Yes ✨
PMC_CAP_PRECISE — No 🙈
PMC_CAP_SYSTEM — Yes ✨
PMC_CAP_TAGGING — No 🙈
PMC_CAP_THRESHOLD — Yes ✨
PMC_CAP_USER — Yes ✨
PMC_CAP_WRITE — Yes ✨

💅 Event Qualifiers 💅

so the event specifiers for these PMCs support the following common qualifiers — think of these as the little add-ons you can sprinkle on your event, like accessories for your outfit 🎀

any — count matching events seen on any logical processor in a package. go wherever the events are, no loyalty 💫
cmask=value — configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to value. it's a little threshold gate, very picky, we respect it.
edge — configure the PMC to count the number of de-asserted → asserted transitions of the conditions expressed by the other qualifiers. and if you specify it, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. one and done, no double counting 💅
inv — invert the sense of comparison when the cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the cmask qualifier. it's the flip side, the plot twist 😭
os — configure the PMC to count events happening at processor privilege level 0. kernel business only 🔒
usr — configure the PMC to count events occurring at privilege levels 1, 2 or 3. user-space girlies represent 🫶

If neither of the os or usr qualifiers are specified, the default is to enable both. so like, no gatekeeping by default, love that for us.

now some events need extra specificity, and they use extra qualifiers. here we go:

Events that require core-specificity use an additional qualifier core=core, where core is one of:

all — measure event conditions on all cores 🌈
this — measure event conditions on this core 💫

The default is this.

Events that require an agent qualifier use an additional qualifier agent=agent, where agent is one of:

this — measure events associated with this bus agent 🚌
any — measure events caused by any bus agent 🚌🚌🚌

The default is this.

Events that require a hardware prefetch qualifier use an additional qualifier prefetch=prefetch, where prefetch is one of:

both — include all prefetches ✨
only — only count hardware prefetches 🎯
exclude — exclude hardware prefetches 🙅

The default is both.

Events that require a cache coherence qualifier use an additional qualifier cachestate=state, where state contains one or more of the following letters (mix and match, it's a whole alphabet vibe):

e — count cache lines in the exclusive state 👑
i — count cache lines in the invalid state 💀
m — count cache lines in the modified state 🔥
s — count cache lines in the shared state 🫶

The default is eims.

Events that require a snoop response qualifier use an additional qualifier snoopresponse=response, where response comprises the following keywords separated by + signs:

clean — measure CLEAN responses 🧼
hit — measure HIT responses 🎯
hitm — measure HITM responses 💥

The default is to measure all the above responses.

Events that require a snoop type qualifier use an additional qualifier snooptype=type, where type comprises one of the following keywords:

cmp2i — measure CMP2I snoops 👀
cmp2s — measure CMP2S snoops 👀

The default is to measure both snoops.

🌟 Event Specifiers (Programmable PMCs) 🌟

Atom programmable PMCs support the following events — and yes, we're doing all of them. buckle up bestie, this is the main character section 👑

BACLEARS — (Event E6H, Umask 01H) The number of times the front end is resteered. 🔄
BOGUS_BR — (Event E4H, Umask 00H) The number of byte sequences mistakenly detected as taken branch instructions. not a real branch, embarrassing 🙈
BR_BAC_MISSP_EXEC — (Event 8AH, Umask 00H) The number of branch instructions that were mispredicted when decoded. 😭
BR_CALL_MISSP_EXEC — (Event 93H, Umask 00H) The number of mispredicted CALL instructions that were executed. 📞💀
BR_CALL_EXEC — (Event 92H, Umask 00H) The number of CALL instructions executed. 📞
BR_CND_EXEC — (Event 8BH, Umask 00H) The number of conditional branches executed, but not necessarily retired. like, they showed up, doesn't mean they stayed ✨
BR_CND_MISSP_EXEC — (Event 8CH, Umask 00H) The number of mispredicted conditional branches executed. 😭
BR_IND_CALL_EXEC — (Event 94H, Umask 00H) The number of indirect CALL instructions executed. 📞🌀
BR_IND_EXEC — (Event 8DH, Umask 00H) The number of indirect branch instructions executed. 🌀
BR_IND_MISSP_EXEC — (Event 8EH, Umask 00H) The number of mispredicted indirect branch instructions executed. 🌀😭
BR_INST_DECODED — (Event E0H, Umask 01H) The number of branch instructions decoded. 🔍
BR_INST_EXEC — (Event 88H, Umask 00H) The number of branches executed, but not necessarily retired. again — executed ≠ retired, keep that distinction in your notes bestie 📝
BR_INST_RETIRED.ANY — (Event C4H, Umask 00H) (Alias "Branch Instruction Retired") The number of branch instructions retired. This is an architectural performance event. very official, very canon 👑
BR_INST_RETIRED.ANY1 — (Event C4H, Umask 0FH) The number of branch instructions retired that were mispredicted. 😭
BR_INST_RETIRED.MISPRED — (Event C5H, Umask 00H) (Alias "Branch Misses Retired") The number of mispredicted branch instructions retired. This is an architectural performance event. 👑
BR_INST_RETIRED.MISPRED_NOT_TAKEN — (Event C4H, Umask 02H) The number of not taken branch instructions retired that were mispredicted. 😭🙅
BR_INST_RETIRED.MISPRED_TAKEN — (Event C4H, Umask 08H) The number taken branch instructions retired that were mispredicted. 😭✅
BR_INST_RETIRED.PRED_NOT_TAKEN — (Event C4H, Umask 01H) The number of not taken branch instructions retired that were correctly predicted. 🎯🙅
BR_INST_RETIRED.PRED_TAKEN — (Event C4H, Umask 04H) The number of taken branch instructions retired that were correctly predicted. 🎯✅
BR_INST_RETIRED.TAKEN — (Event C4H, Umask 0CH) The number of taken branch instructions retired. ✅
BR_MISSP_EXEC — (Event 89H, Umask 00H) The number of mispredicted branch instructions that were executed. 😭
BR_RET_MISSP_EXEC — (Event 90H, Umask 00H) The number of mispredicted RET instructions executed. ↩️😭
BR_RET_BAC_MISSP_EXEC — (Event 91H, Umask 00H) The number of RET instructions executed that were mispredicted at decode time. ↩️🔍😭
BR_RET_EXEC — (Event 8FH, Umask 00H) The number of RET instructions executed. ↩️
BR_TKN_BUBBLE_1 — (Event 97H, Umask 00H) The number of branch predicted taken with bubble 1. 🫧
BR_TKN_BUBBLE_2 — (Event 98H, Umask 00H) The number of branch predicted taken with bubble 2. 🫧🫧
BUSQ_EMPTY [,core=core] — (Event 7DH) The number of cycles during which the core did not have any pending transactions in the bus queue. empty queue, peaceful era 🧘
BUS_BNR_DRV [,agent=agent] — (Event 61H) The number of Bus Not Ready signals asserted on the bus. This event is thread-independent. 🚌
BUS_DATA_RCV [,core=core] — (Event 64H) The number of bus cycles during which the processor is receiving data. This event is thread-independent. 🚌📥
BUS_DRDY_CLOCKS [,agent=agent] — (Event 62H) The number of bus cycles during which the Data Ready signal is asserted on the bus. This event is thread-independent. 🚌⏰
BUS_HIT_DRV [,agent=agent] — (Event 7AH) The number of bus cycles during which the processor drives the HIT# pin. This event is thread-independent. 🚌🎯
BUS_HITM_DRV [,agent=agent] — (Event 7BH) The number of bus cycles during which the processor drives the HITM# pin. This event is thread-independent. 🚌💥
BUS_IO_WAIT [,core=core] — (Event 7FH) The number of core cycles during which I/O requests wait in the bus queue. the waiting room energy 🪑
BUS_LOCK_CLOCKS [,agent=agent] [,core=core] — (Event 63H) The number of bus cycles during which the LOCK signal was asserted on the bus. This event is thread independent. 🔒
BUS_REQUEST_OUTSTANDING [,agent=agent] [,core=core] — (Event 60H) The number of pending full cache line read transactions on the bus occurring in each cycle. This event is thread independent. 🚌📋
BUS_TRANS_P [,agent=agent] [,core=core] — (Event 6BH) The number of partial bus transactions. 🚌
BUS_TRANS_IFETCH [,agent=agent] [,core=core] — (Event 68H) The number of instruction fetch full cache line bus transactions. 🚌🔍
BUS_TRANS_INVAL [,agent=agent] [,core=core] — (Event 69H) The number of invalidate bus transactions. 🚌🗑️
BUS_TRANS_PWR [,agent=agent] [,core=core] — (Event 6AH) The number of partial write bus transactions. 🚌✍️
BUS_TRANS_DEF [,agent=agent] [,core=core] — (Event 6DH) The number of deferred bus transactions. 🚌⏳
BUS_TRANS_BURST [,agent=agent] [,core=core] — (Event 6EH) The number of burst transactions. 🚌💥
BUS_TRANS_MEM [,agent=agent] [,core=core] — (Event 6FH) The number of memory bus transactions. 🚌🧠
BUS_TRANS_ANY [,agent=agent] [,core=core] — (Event 70H) The number of bus transactions of any kind. 🚌🌈
BUS_TRANS_BRD [,agent=agent] [,core=core] — (Event 65H) The number of burst read transactions. 🚌📖
BUS_TRANS_IO [,agent=agent] [,core=core] — (Event 6CH) The number of completed I/O bus transactions due to IN and OUT instructions. 🚌📥📤
BUS_TRANS_RFO [,agent=agent] [,core=core] — (Event 66H) how many Read For Ownership bus transactions went down. bestie's cache is claiming a line for itself, iconic behavior 💅
BUS_TRANS_WB [,agent=agent] [,core=core] — (Event 67H) the number of explicit write-back bus transactions, and the reason is dirty line evictions. the data was messy so it had to go 🧹
CMP_SNOOP [,core=core] [,snooptype=snoop] — (Event 78H) how many times the L1 data cache got snooped on by the other core in the same processor. imagine being watched like that, no privacy fr 😭
CPU_CLK_UNHALTED.BUS — (Event 3CH, Umask 01H) (Alias "Unhalted Reference Cycles") bus cycles where the core is not in the halt state. this one is an architectural performance event, so it's kind of a big deal 👑
CPU_CLK_UNHALTED.CORE_P — (Event 3CH, Umask 00H) (Alias "Unhalted Core Cycles") core cycles while the core is not in a halt state. also an architectural performance event ✨
CPU_CLK_UNHALTED.NO_OTHER — (Event 3CH, Umask 02H) bus cycles where the core stays unhalted and the other core is halted. one of them is working, the other one is literally asleep 💀
CYCLES_DIV_BUSY — (Event 14H, Umask 01H) cycles the divider is busy. divider era, we love to see it 🍓
CYCLES_INT_MASKED.CYCLES_INT_MASKED — (Event C6H, Umask 01H) cycles during which interrupts are disabled. do not disturb mode, periodt 🙈
CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED — (Event C6H, Umask 02H) cycles where there were pending interrupts while interrupts were disabled. they were queued up waiting and nobody answered the door 😭
CYCLES_L1I_MEM_STALLED — (Event 86H, Umask 00H) cycles where an instruction fetch stalls. the fetch said "hold on" 🫶
DATA_TLB_MISSES.DTLB_MISS — (Event 08H, Umask 07H) the number of memory access that missed the Data TLB. not in the table bestie, awkward 💀
DATA_TLB_MISSES.DTLB_MISS_LD — (Event 08H, Umask 05H) the number of loads that missed the Data TLB.
DATA_TLB_MISSES.DTLB_MISS_ST — (Event 08H, Umask 06H) the number of stores that missed the Data TLB.
DATA_TLB_MISSES.UTLB_MISS_LD — (Event 08H, Umask 09H) the number of loads that missed the UTLB.
DELAYED_BYPASS.FP — (Event 19H, Umask 00H) floating point operations that used data immediately after that data was generated by a non floating point execution unit. no waiting, zero patience, main character energy 🔥
DELAYED_BYPASS.LOAD — (Event 19H, Umask 01H) the number of delayed bypass penalty cycles that a load operation incurred. penalties, in this economy 😭
DELAYED_BYPASS.SIMD — (Event 19H, Umask 02H) how many times SIMD operations use data immediately after the data was generated by a non-SIMD execution unit.
DIV — (Event 13H, Umask 00H) the number of divide operations executed. heads up: this event is only available on PMC1 👀
DIV.AR — (Event 13H, Umask 81H) the number of divide operations retired. retired like a queen leaving the stage 👑
DIV.S — (Event 13H, Umask 01H) the number of divide operations executed.
DTLB_MISSES.ANY — (Event 08H, Umask 01H) Data TLB misses, and yes that includes the misses that result from speculative accesses. we count the bold guesses too 🎀
DTLB_MISSES.L0_MISS_LD — (Event 08H, Umask 04H) level 0 DTLB misses due to load operations.
DTLB_MISSES.MISS_LD — (Event 08H, Umask 02H) Data TLB misses due to load operations.
DTLB_MISSES.MISS_ST — (Event 08H, Umask 08H) Data TLB misses due to store operations.
EIST_TRANS — (Event 3AH, Umask 00H) the number of Enhanced Intel SpeedStep Technology transitions. glow-up after glow-up 🌈
ESP.ADDITIONS — (Event ABH, Umask 02H) the number of automatic additions to the %esp register. stack grows, we cheer 🌸
ESP.SYNCH — (Event ABH, Umask 01H) how many times the %esp register was explicitly used in an address expression after it's implicitly used by a PUSH or POP instruction. messy but valid 💅
EXT_SNOOP [,agent=agent] [,snoopresponse=response] — (Event 77H) the number of snoop responses to bus transactions. replying to the group chat of hardware 🫶
FP_ASSIST — (Event 11H, Umask 01H) floating point operations executed that needed a microcode assist, and that includes speculatively executed instructions. asking the group chat for help mid-quest 😭
FP_ASSIST.AR — (Event 11H, Umask 81H) floating point operations retired that needed a microcode assist.
FP_COMP_OPS_EXE — (Event 10H, Umask 00H) the number of floating point computational micro-ops executed. available only on PMC0, iykyk 🎀
FP_MMX_TRANS_TO_FP — (Event CCH, Umask 02H) transitions from MMX instructions to floating point instructions. switching lanes, slay ✨
FP_MMX_TRANS_TO_MMX — (Event CCH, Umask 01H) transitions from floating point instructions to MMX instructions.
HW_INT_RCV — (Event C8H, Umask 00H) the number of hardware interrupts received. notifications: on 🔔
ICACHE.ACCESSES — (Event 80H, Umask 03H) the number of instruction fetches.
ICACHE.MISSES — (Event 80H, Umask 02H) instruction fetches that miss the instruction cache. not found bestie 💀
IDLE_DURING_DIV — (Event 18H, Umask 00H) cycles where the divider is busy and no other execution unit or load operation was in progress. this event is available only on PMC0 💜
ILD_STALL — (Event 87H, Umask 00H) cycles the instruction length decoder stalled due to a length changing prefix. the prefix changed and the decoder was like "wait—" 🙈
INST_QUEUE.FULL — (Event 83H, Umask 02H) cycles during which the instruction queue is full. no vacancy, we're booked 💅
INST_RETIRED.ANY_P — (Event C0H, Umask 00H) (Alias "Instruction Retired") the number of instructions retired. this is an architectural performance event, so it's basically famous 👑
INST_RETIRED.LOADS — (Event C0H, Umask 01H) retired instructions that contained a load operation.
INST_RETIRED.OTHER — (Event C0H, Umask 04H) retired instructions that did not contain a load or a store operation. the "other" girlies get counted too 🎀
INST_RETIRED.STORES — (Event C0H, Umask 02H) retired instructions that contained a store operation.
ITLB.FLUSH — (Event 82H, Umask 04H) the number of ITLB flushes. flush it, it's giving fresh start 🚽✨
ITLB.LARGE_MISS — (Event 82H, Umask 10H) instruction fetches from large pages that miss the ITLB.
ITLB.MISSES — (Event 82H, Umask 02H) instruction fetches from both large and small pages that miss the ITLB.
ITLB.SMALL_MISS — (Event 82H, Umask 02H) instruction fetches from small pages that miss the ITLB.
ITLB_MISS_RETIRED — (Event C9H, Umask 00H) retired instructions that missed the ITLB when they were fetched. missed at fetch time, retired anyway. resilient 💪
L1D_ALL_REF — (Event 43H, Umask 01H) references to L1 data cache, counting loads and stores of to all memory types. (yes, that's verbatim how it reads, don't come for me 😭)
L1D_ALL_CACHE_REF — (Event 43H, Umask 02H) data reads and writes to cacheable memory.
L1D_CACHE_LOCK [,cachestate=state] — (Event 42H) the number of locked reads from cacheable memory. 🔒
L1D_CACHE_LOCK_DURATION — (Event 42H, Umask 10H) cycles during which any cache line is locked by any locking instruction. how long the lock is being held, no line cutting 🫶
L1D_CACHE.LD — (Event 40H, Umask 21H) data reads from cacheable memory.
L1D_CACHE.ST — (Event 41H, Umask 22H) data writes to cacheable memory.
L1D_M_EVICT — (Event 47H, Umask 00H) modified cache lines evicted from L1 data cache. evicted, sorry bestie, the lease ended 😭
L1D_M_REPL — (Event 46H, Umask 00H) modified lines allocated in L1 data cache. new line just moved in 🏠
L1D_PEND_MISS — (Event 48H, Umask 00H) the total number of outstanding L1 data cache misses at any clock. pending, pending, pending… 🕐
L1D_PREFETCH.REQUESTS — (Event 4EH, Umask 10H) how many times L1 data cache requested to prefetch a data cache line. manifestation, but for cache 🔮
L1D_REPL — (Event 45H, Umask 0FH) the number of lines brought into L1 data cache.
L1D_SPLIT.LOADS — (Event 49H, Umask 01H) load operations that span two cache lines. two homes, both valid 💅
L1D_SPLIT.STORES — (Event 49H, Umask 02H) store operations that span two cache lines.
L1I_MISSES — (Event 81H, Umask 00H) the number of instruction fetch unit misses.
L1I_READS — (Event 80H, Umask 00H) the number of instruction fetches.
L2_ADS [,core=core] — (Event 21H) cycles the L2 address bus is in use. address bus is booked and busy 📞
L2_DBUS_BUSY_RD [,core=core] — (Event 23H) core cycles where the L2 data bus is busy transferring data to the core. data in transit, tracking says out for delivery 📦
L2_IFETCH [,cachestate=state] [,core=core] — (Event 28H) instruction cache line requests coming from the instruction fetch unit.
L2_LD [,cachestate=state] [,core=core] [,prefetch=prefetch] — (Event 29H) L2 cache read requests from L1 cache and L2 prefetchers. a whole crowd asking for data 🫶
L2_LINES_IN [,core=core] [,prefetch=prefetch] — (Event 24H) cache lines allocated in L2 cache.
L2_LINES_OUT [,core=core] [,prefetch=prefetch] — (Event 26H) L2 cache lines evicted.
L2_LOCK [,cachestate=state] [,core=core] — (Event 2BH) locked accesses to cache lines that miss L1 data cache. 🔐
L2_M_LINES_IN [,core=core] — (Event 25H) the number of L2 cache line modifications.
L2_M_LINES_OUT [,core=core] [,prefetch=prefetch] — (Event 27H) modified lines evicted from L2 cache. dirty and now it's gone 💀
L2_NO_REQ [,core=core] — (Event 32H) cycles where no L2 cache requests were pending from a core. silence. blessed silence. 🕊️
L2_REJECT_BUSQ [,cachestate=state] [,core=core] [,prefetch=prefetch] — (Event 30H) L2 cache requests that were rejected. left on read 😭
L2_RQSTS [,cachestate=state] [,core=core] [,prefetch=prefetch] — (Event 2EH) completed L2 cache requests.
L2_RQSTS.SELF.DEMAND.I_STATE — (Event 2EH, Umask 41H) (Alias "LLC Misses") completed L2 cache demand requests from this core that missed the L2 cache. this one's an architectural performance event, so yeah, it's kind of a celebrity 👑
L2_RQSTS.SELF.DEMAND.MESI — (Event 2EH, Umask 4FH) (Alias "LLC References") completed L2 cache demand requests from this core.
L2_ST [,cachestate=state] [,core=core] — (Event 2AH) store operations that miss the L1 cache and request data from the L2 cache. went downstairs to ask for the data fr 🚶‍♀️
LOAD_BLOCK.L1D — (Event 03H, Umask 20H) how many loads got blocked by the L1 data cache, bestie. rude of it tbh.
LOAD_BLOCK.OVERLAP_STORE — (Event 03H, Umask 08H) the count of loads that partially overlap an earlier store, or that are aliased with a previous store.
LOAD_BLOCK.STA — (Event 03H, Umask 02H) loads blocked by preceding stores whose address hasn't even been calculated yet. the suspense 💀
LOAD_BLOCK.STD — (Event 03H, Umask 04H) loads blocked by preceding stores to the same address whose data value is not known. so close and yet so far 😭
LOAD_BLOCK.UNTIL_RETIRE — (Event 03H, Umask 10H) how many load operations were blocked until retirement.
LOAD_HIT_PRE — (Event 4CH, Umask 00H) loads that conflicted with an prefetch to the same cache line. yes that's the original phrasing, it's iconic, don't touch it 💅
MACHINE_CLEARS.SMC — (Event C3H, Umask 01H) how many times a program writes to a code section.
MACHINE_NUKES.MEM_ORDER — (Event C3H, Umask 04H) how many times the execution pipeline got restarted because of a memory ordering conflict or a memory disambiguation misprediction. machine nukes, literally 🌸
MACRO_INSTS.ALL_DECODED — (Event AAH, Umask 03H) the number of instructions decoded.
MACRO_INSTS.CISC_DECODED — (Event AAH, Umask 02H) the number of complex instructions decoded.
MEMORY_DISAMBIGUATION.RESET — (Event 09H, Umask 01H) how many cycles memory disambiguation misprediction occurs during.
MEMORY_DISAMBIGUATION.SUCCESS — (Event 09H, Umask 02H) the load operations that were successfully disambiguated. slay ✨
MEM_LOAD_RETIRED.DTLB_MISS — (Event CBH, Umask 04H) retired load operations that missed the DTLB.
MEM_LOAD_RETIRED.L2_MISS — (Event CBH, Umask 02H) retired load operations that miss L2 cache.
MEM_LOAD_RETIRED.L2_HIT — (Event CBH, Umask 01H) retired load operations that hit L2 cache.
MEM_LOAD_RETIRED.L2_LINE_MISS — (Event CBH, Umask 08H) load operations that missed L2 cache and caused a bus request. double trouble 😭
MUL — (Event 12H, Umask 00H) the number of multiply operations executed. ⚠️ heads up: this event is only available on PMC1.
MUL.AR — (Event 12H, Umask 81H) the number of multiply operations retired.
MUL.S — (Event 12H, Umask 01H) the number of multiply operations executed.
PAGE_WALKS.WALKS — (Event 0CH, Umask 03H) page walks executed due to an ITLB or DTLB miss. going for a lil walk 🚶‍♀️
PAGE_WALKS.CYCLES — (Event 0CH, Umask 03H) how many cycles got spent in a page walk caused by an ITLB or DTLB miss.
PREF_RQSTS_DN — (Event F8H, Umask 00H) downward prefetches issued from the Data Prefetch Logic unit to L2 cache.
PREF_RQSTS_UP — (Event F0H, Umask 00H) upward prefetches issued from the Data Prefetch Logic unit to L2 cache.
PREFETCH.PREFETCHNTA — (Event 07H, Umask 08H) the number of PREFETCHNTA instructions executed.
PREFETCH.PREFETCHT0 — (Event 07H, Umask 01H) the number of PREFETCHT0 instructions executed.
PREFETCH.SW_L2 — (Event 07H, Umask 06H) the number of PREFETCHT1 and PREFETCHT2 instructions executed. two for one 🫶
RAT_STALLS.ANY — (Event D2H, Umask 0FH) stall cycles caused by any of RAT_STALLS.FLAGS, RAT_STALLS.FPSW, RAT_STALLS.PARTIAL and RAT_STALLS.ROB_READ_PORT. the whole squad 🎀
RAT_STALLS.FLAGS — (Event D2H, Umask 04H) cycles execution stalled because of a flag register induced stall.
RAT_STALLS.FPSW — (Event D2H, Umask 08H) how many times the floating point status word was written.
RAT_STALLS.PARTIAL_CYCLES — (Event D2H, Umask 02H) extra cycles of instruction execution latency from using a register that was partially written by previous instructions. the way that costs you cycles… 💀
RAT_STALLS.ROB_READ_PORT — (Event D2H, Umask 01H) cycles when ROB read port stalls occurred.
RESOURCE_STALLS.ANY — (Event DCH, Umask 1FH) cycles during which any resource related stall happened.
RESOURCE_STALLS.BR_MISS_CLEAR — (Event DCH, Umask 10H) cycles stalled due to branch misprediction.
RESOURCE_STALLS.FPCW — (Event DCH, Umask 08H) cycles stalled due to writing the floating point control word.
RESOURCE_STALLS.LD_ST — (Event DCH, Umask 04H) cycles during which the number of loads and stores in the pipeline exceeded their limits. too much going on fr fr
RESOURCE_STALLS.ROB_FULL — (Event DCH, Umask 01H) cycles when the reorder buffer was full.
RESOURCE_STALLS.RS_FULL — (Event DCH, Umask 02H) cycles during which the RS was full.
RS_UOPS_DISPATCHED — (Event A0H, Umask 00H) the number of micro-ops dispatched for execution.
RS_UOPS_DISPATCHED.PORT0 — (Event A1H, Umask 01H) cycles micro-ops were dispatched for execution on port 0.
RS_UOPS_DISPATCHED.PORT1 — (Event A1H, Umask 02H) cycles micro-ops were dispatched for execution on port 1.
RS_UOPS_DISPATCHED.PORT2 — (Event A1H, Umask 04H) cycles micro-ops were dispatched for execution on port 2.
RS_UOPS_DISPATCHED.PORT3 — (Event A1H, Umask 08H) cycles micro-ops were dispatched for execution on port 3.
RS_UOPS_DISPATCHED.PORT4 — (Event A1H, Umask 10H) cycles micro-ops were dispatched for execution on port 4.
RS_UOPS_DISPATCHED.PORT5 — (Event A1H, Umask 20H) cycles micro-ops were dispatched for execution on port 5. five ports, five icons 💅✨🎀🦋🌸
SB_DRAIN_CYCLES — (Event 04H, Umask 01H) cycles while the store buffer is draining.
SEGMENT_REG_LOADS.ANY — (Event 06H, Umask 00H) the number of segment register loads.
SEG_REG_RENAMES.ANY — (Event D5H, Umask 0FH) how many times any segment register was renamed.
SEG_REG_RENAMES.DS — (Event D5H, Umask 02H) how many times the %ds register is renamed.
SEG_REG_RENAMES.ES — (Event D5H, Umask 01H) how many times the %es register is renamed.
SEG_REG_RENAMES.FS — (Event D5H, Umask 04H) how many times the %fs register is renamed.
SEG_REG_RENAMES.GS — (Event D5H, Umask 08H) how many times the %gs register is renamed.
SEG_RENAME_STALLS.ANY — (Event D4H, Umask 0FH) stalls due to lack of resource to rename any segment register.
SEG_RENAME_STALLS.DS — (Event D4H, Umask 02H) stalls due to lack of renaming resources for the %ds register.
SEG_RENAME_STALLS.ES — (Event D4H, Umask 01H) stalls due to lack of renaming resources for the %es register.
SEG_RENAME_STALLS.FS — (Event D4H, Umask 04H) stalls due to lack of renaming resources for the %fs register.
SEG_RENAME_STALLS.GS — (Event D4H, Umask 08H) stalls due to lack of renaming resources for the %gs register.
SIMD_ASSIST — (Event CDH, Umask 00H) the number of SIMD assists invoked.
SIMD_COMP_INST_RETIRED.PACKED_DOUBLE — (Event CAH, Umask 04H) then number of computational SSE2 packed double precision instructions retired. (yes, "then" — the original said it, we're keeping it, it's part of the lore 🎀)
SIMD_COMP_INST_RETIRED.PACKED_SINGLE — (Event CAH, Umask 01H) then number of computational SSE2 packed single precision instructions retired.
SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE — (Event CAH, Umask 08H) then number of computational SSE2 scalar double precision instructions retired.
SIMD_COMP_INST_RETIRED.SCALAR_SINGLE — (Event CAH, Umask 02H) then number of computational SSE2 scalar single precision instructions retired.
SIMD_INSTR_RETIRED — (Event CEH, Umask 00H) retired SIMD instructions that use MMX registers. throwback 👑
SIMD_INST_RETIRED.ANY — (Event C7H, Umask 1FH) the number of streaming SIMD instructions retired.
SIMD_INST_RETIRED.PACKED_DOUBLE — (Event C7H, Umask 04H) SSE2 packed double precision instructions retired.
SIMD_INST_RETIRED.PACKED_SINGLE — (Event C7H, Umask 01H) SSE packed single precision instructions retired.
SIMD_INST_RETIRED.SCALAR_DOUBLE — (Event C7H, Umask 08H) SSE2 scalar double precision instructions retired.
SIMD_INST_RETIRED.SCALAR_SINGLE — (Event C7H, Umask 02H) SSE scalar single precision instructions retired.
SIMD_INST_RETIRED.VECTOR — (Event C7H, Umask 10H) SSE2 vector instructions retired.
SIMD_SAT_INSTR_RETIRED — (Event CFH, Umask 00H) saturated arithmetic SIMD instructions retired.
SIMD_SAT_UOP_EXEC.AR — (Event B1H, Umask 80H) SIMD saturated arithmetic micro-ops retired.
SIMD_SAT_UOP_EXEC.S — (Event B1H, Umask 00H) SIMD saturated arithmetic micro-ops executed.
SIMD_UOPS_EXEC.AR — (Event B0H, Umask 80H) the number of SIMD micro-ops retired.
SIMD_UOPS_EXEC.S — (Event B0H, Umask 00H) the number of SIMD micro-ops executed.
SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR — (Event B3H, Umask A0H) SIMD packed arithmetic micro-ops executed.
SIMD_UOP_TYPE_EXEC.ARITHMETIC.S — (Event B3H, Umask 20H) SIMD packed arithmetic micro-ops executed.
SIMD_UOP_TYPE_EXEC.LOGICAL.AR — (Event B3H, Umask 90H) SIMD packed logical micro-ops executed.
SIMD_UOP_TYPE_EXEC.LOGICAL.S — (Event B3H, Umask 10H) SIMD packed logical micro-ops executed.
SIMD_UOP_TYPE_EXEC.MUL.AR — (Event B3H, Umask 81H) SIMD packed multiply micro-ops retired.
SIMD_UOP_TYPE_EXEC.MUL.S — (Event B3H, Umask 01H) SIMD packed multiply micro-ops executed.
SIMD_UOP_TYPE_EXEC.PACK.AR — (Event B3H, Umask 84H) the number of SIMD pack micro-ops retired.
SIMD_UOP_TYPE_EXEC.PACK.S — (Event B3H, Umask 04H) how many SIMD pack micro-ops got executed 🎀
SIMD_UOP_TYPE_EXEC.SHIFT.AR — (Event B3H, Umask 82H) the count of SIMD packed shift micro-ops that retired ✨
SIMD_UOP_TYPE_EXEC.SHIFT.S — (Event B3H, Umask 02H) how many SIMD packed shift micro-ops were executed 💅
SIMD_UOP_TYPE_EXEC.UNPACK.AR — (Event B3H, Umask 88H) the number of SIMD unpack micro-ops executed 🌸
SIMD_UOP_TYPE_EXEC.UNPACK.S — (Event B3H, Umask 08H) same vibe, unpack micro-ops executed, count 'em 🦋
SNOOP_STALL_DRV [,agent=agent] [,core=core] — (Event 7EH) how many times the bus stalled waiting on snoops 😭 this one is thread-independent, so don't go attributing it to a thread, bestie
SSE_PRE_EXEC.L2 — (Event 07H, Umask 02H) the number of PREFETCHT1 instructions executed 👑
SSE_PRE_EXEC.STORES — (Event 07H, Umask 03H) how many times SSE non-temporal store instructions were executed 🔥
SSE_PRE_MISS.L1 — (Event 4BH, Umask 01H) how many times PREFETCHT0 executed and missed all cache levels 💀 brutal
SSE_PRE_MISS.L2 — (Event 4BH, Umask 02H) how many times PREFETCHT1 executed and missed all cache levels 😬
SSE_PRE_MISS.NTA — (Event 4BH, Umask 00H) how many times PREFETCHNTA executed and missed all cache levels 🙈
STORE_BLOCK.ORDER — (Event 04H, Umask 02H) the number of cycles spent while a store was waiting for another store to be globally observed ⏳
STORE_BLOCK.SNOOP — (Event 04H, Umask 08H) the number of cycles while a store was blocked because of a conflict with an internal or external snoop 🚧
STORE_FORWARDS.GOOD — (Event 02H, Umask 81H) how many times stored data got forwarded directly to a load — we love a shortcut 💖
THERMAL_TRIP — (Event 3BH, Umask C0H) the number of thermal trips 🌡️ she's hot, literally
UOPS_RETIRED.LD_IND_BR — (Event C2H, Umask 01H) micro-ops retired that fused a load with another operation 🧚
UOPS_RETIRED.STD_STA — (Event C2H, Umask 02H) store address calculations that fused into one micro-op ✨
UOPS_RETIRED.MACRO_FUSION — (Event C2H, Umask 04H) how many times retired instruction pairs were fused into one micro-op 🫶 iconic behavior
UOPS_RETIRED.FUSED — (Event C2H, Umask 07H) the number of fused micro-ops retired 💅
UOPS_RETIRED.NON_FUSED — (Event C2H, Umask 8H) the number of non-fused micro-ops retired 🍓
UOPS_RETIRED.ANY — (Event C2H, Umask 10H) the number of micro-ops retired, periodt 👑
X87_COMP_OPS_EXE.ANY.AR — (Event 10H, Umask 81H) the number of x87 floating-point computational micro-ops retired 🌈
X87_COMP_OPS_EXE.ANY.S — (Event 10H, Umask 01H) the number of x87 floating-point computational micro-ops executed ⭐
X87_OPS_RETIRED.ANY — (Event C1H, Umask FEH) the number of floating point computational instructions retired 🔥
X87_OPS_RETIRED.FXCH — (Event C1H, Umask 01H) the number of FXCH instructions retired 🎀

🏷️ Event Name Aliases

okay so this next part is lowkey the bestie-friendly cheat sheet 🫶 here's the mapping between the PMC-independent aliases that the Performance Counters Library (libpmc, -lpmc) supports and the actual hardware events underneath them on these CPUs:

branches → BR_INST_RETIRED.ANY → PMC_CLASS_IAP
branch-mispredicts → BR_INST_RETIRED.MISPRED → PMC_CLASS_IAP
ic-misses → ICACHE.MISSES → PMC_CLASS_IAP
instructions → INST_RETIRED.ANY_P → PMC_CLASS_IAF
interrupts → HW_INT_RCV → PMC_CLASS_IAP
unhalted-cycles → CPU_CLK_UNHALTED.CORE_P → PMC_CLASS_IAF

👀 SEE ALSO

go read these next, fr fr:

pmc(3), pmc.amd(3), pmc.atomsilvermont(3), pmc.core(3), pmc.core2(3), pmc.iaf(3), pmc.soft(3), pmc.tsc(3), pmc_cpuinfo(3), pmclog(3), hwpmc(4)

📜 HISTORY

The pmc library first appeared in FreeBSD 6.0 ✨ she's been around a minute, respect her

💖 AUTHORS

The Performance Counters Library (libpmc, -lpmc) library was written by Joseph Koshy <jkoshy@FreeBSD.org> 👑 ty king

and that's a wrap bestie 💅 this page was served up by Debian, dated March 20, 2014, and it lives at PMC.ATOM(3) — go forth and count them counters 🦋✨

📦 where this page comes from

freebsd 15.1: base 15.1
💖 girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on 2026-11-04: a language model's rewrite of the original, under its terms