PMC.SANDYBRIDGE(3)

🎀 NAME 🎀

pmc.sandybridge — measurement events for Intel Sandy Bridge family CPUs. Yes bestie, from the Library Functions Manual, and it’s giving “let’s actually measure what this silicon is doing.” ✨

🌸 LIBRARY 🌸

Performance Counters Library (libpmc, -lpmc) — that’s the whole point, link it and go.

✨ SYNOPSIS ✨

#include <pmc.h>

💅 DESCRIPTION 💅

Okay so: Intel Sandy Bridge CPUs contain PMCs conforming to the version 3 of the Intel performance measurement architecture. These CPUs may contain up to three classes of PMCs:

• PMC_CLASS_IAF — Fixed-function counters that count only one hardware event per counter.
• PMC_CLASS_IAP — Programmable counters that may be configured to count one of a defined set of hardware events.
• PMC_CLASS_TSC — These PMCs are documented in pmc.tsc(3).

The number of PMCs available in each class and their widths need to be determined at run time by calling pmc_cpuinfo(3). No guessing, bestie. 🫶

Intel Sandy Bridge PMCs are documented in “Volume 3B: System Programming Guide, Part 2”, Intel(R) 64 and IA-32 Architectures Software Developers Manual, Order Number: 253669-039US, Intel Corporation, May 2011.

🦋 SANDY BRIDGE FIXED FUNCTION PMCS 🦋

These PMCs and their supported events are documented in pmc.iaf(3).

🫶 SANDY BRIDGE PROGRAMMABLE PMCS 🫶

The programmable PMCs support the following capabilities:

• PMC_CAP_CASCADE — No
• PMC_CAP_EDGE — Yes
• PMC_CAP_INTERRUPT — Yes
• PMC_CAP_INVERT — Yes
• PMC_CAP_READ — Yes
• PMC_CAP_PRECISE — No
• PMC_CAP_SYSTEM — Yes
• PMC_CAP_TAGGING — No
• PMC_CAP_THRESHOLD — Yes
• PMC_CAP_USER — Yes
• PMC_CAP_WRITE — Yes

💫 Event Qualifiers 💫

Event specifiers for these PMCs support the following common qualifiers:

• rsp=value — Configure the Off-core Response bits.
  • REQ_DMND_DATA_RD — Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches.
  • REQ_DMND_RFO — Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches.
  • REQ_DMND_IFETCH — Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches.
  • REQ_WB — Counts the number of writeback (modified to exclusive) transactions.
  • REQ_PF_DATA_RD — Counts the number of data cacheline reads generated by L2 prefetchers.
  • REQ_PF_RFO — Counts the number of RFO requests generated by L2 prefetchers.
  • REQ_PF_IFETCH — Counts the number of code reads generated by L2 prefetchers.
  • REQ_PF_LLC_DATA_RD — L2 prefetcher to L3 for loads.
  • REQ_PF_LLC_RFO — RFO requests generated by L2 prefetcher
  • REQ_PF_LLC_IFETCH — L2 prefetcher to L3 for instruction fetches.
  • REQ_BUS_LOCKS — Bus lock and split lock requests.
  • REQ_STRM_ST — Streaming store requests.
  • REQ_OTHER — Any other request that crosses IDI, including I/O.
  • RES_ANY — Catch all value for any response types.
  • RES_SUPPLIER_NO_SUPP — No Supplier Information available.
  • RES_SUPPLIER_LLC_HITM — M-state initial lookup stat in L3.
  • RES_SUPPLIER_LLC_HITE — E-state.
  • RES_SUPPLIER_LLC_HITS — S-state.
  • RES_SUPPLIER_LLC_HITF — F-state.
  • RES_SUPPLIER_LOCAL — Local DRAM Controller.
  • RES_SNOOP_SNP_NONE — No details on snoop-related information.
  • RES_SNOOP_SNP_NO_NEEDED — No snoop was needed to satisfy the request.
  • RES_SNOOP_SNP_MISS — A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM.
  • RES_SNOOP_HIT_NO_FWD — A snoop was needed and it hits in at least one snooped cache. Hit denotes a cache-line was valid before snoop effect. This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM.
  • RES_SNOOP_HIT_FWD — A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
  • RES_SNOOP_HITM — A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a cache-line was in modified state before effect as a results of snoop. This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD).
  • RES_NON_DRAM — Target was non-DRAM system address. This includes MMIO transactions.
• cmask=value — Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to value.
• edge — Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true.
• inv — Invert the sense of comparison when the “cmask” qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the “cmask” qualifier.
• os — Configure the PMC to count events happening at processor privilege level 0.
• usr — Configure the PMC to count events occurring at privilege levels 1, 2 or 3.

If neither of the “os” or “usr” qualifiers are specified, the default is to enable both.

🌈 Event Specifiers (Programmable PMCs) 🌈

Sandy Bridge programmable PMCs support the following events:

• LD_BLOCKS.DATA_UNKNOWN — Event 03H, Umask 01H: Blocked loads due to store buffer blocks with unknown data.
• LD_BLOCKS.STORE_FORWARD — Event 03H, Umask 02H: Loads blocked by overlapping with store buffer that cannot be forwarded.
• LD_BLOCKS.NO_SR — Event 03H, Umask 08H: # of Split loads blocked due to resource not available.
• LD_BLOCKS.ALL_BLOCK — Event 03H, Umask 10H: Number of cases where any load is blocked but has no DCU miss.
• MISALIGN_MEM_REF.LOADS — Event 05H, Umask 01H: Speculative cache-line split load uops dispatched to L1D.
• MISALIGN_MEM_REF.STORES — Event 05H, Umask 02H: Speculative cache-line split Store-address uops dispatched to L1D.
• LD_BLOCKS_PARTIAL.ADDRESS_ALIAS — Event 07H, Umask 01H: False dependencies in MOB due to partial compare on address.
• LD_BLOCKS_PARTIAL.ALL_STA_BLOCK — Event 07H, Umask 08H: The number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.
• LI DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK — Event 08H, Umask 01H: Misses in all TLB levels that cause a page walk of any page size.
• DTLB_LOAD_MISSES.WALK_COMPLETED — Event 08H, Umask 02H: Misses in all TLB levels that caused page walk completed of any size.
• DTLB_LOAD_MISSES.WALK_DURATION — Event 08H, Umask 04H: Cycle PMH is busy with a walk.
• DTLB_LOAD_MISSES.STLB_HIT — Event 08H, Umask 10H: Number of cache load STLB hits. No page walk.
• INT_MISC.RECOVERY_CYCLES — Event 0DH, Umask 03H: Cycles waiting to recover after Machine Clears or JEClear. Set Cmask = 1. Set Edge to count occurrences
• INT_MISC.RAT_STALL_CYCLES — Event 0DH, Umask 40H: Cycles RAT external stall is sent to IDQ for this thread.
• UOPS_ISSUED.ANY — Event 0EH, Umask 01H: Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1 to count stalled cycles of this core. Set Cmask = 1, Inv = 1 to count stalled cycles
• FP_COMP_OPS_EXE.X87 — Event 10H, Umask 01H: Counts number of X87 uops executed.
• FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE — Event 10H, Umask 10H: Counts number of SSE* double precision FP packed uops executed.
• FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE — Event 10H, Umask 20H: Counts number of SSE* single precision FP scalar uops executed.
• FP_COMP_OPS_EXE.SSE_PACKED_SINGLE — Event 10H, Umask 40H: Counts number of SSE* single precision FP packed uops executed.
• LiFP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE — Event 10H, Umask 80H: Counts number of SSE* double precision FP scalar uops executed.
• SIMD_FP_256.PACKED_SINGLE — Event 11H, Umask 01H: Counts 256-bit packed single-precision floating-point instructions.
• SIMD_FP_256.PACKED_DOUBLE — Event 11H, Umask 02H: Counts 256-bit packed double-precision floating-point instructions.
• ARITH.FPU_DIV_ACTIVE — Event 14H, Umask 01H: Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.
• INSTS_WRITTEN_TO_IQ.INSTS — Event 17H, Umask 01H: Counts the number of instructions written into the IQ every cycle.
• L2_RQSTS.DEMAND_DATA_RD_HIT — Event 24H, Umask 01H: Demand Data Read requests that hit L2 cache.
• L2_RQSTS.ALL_DEMAND_DATA_RD — Event 24H, Umask 03H: Counts any demand and L1 HW prefetch data load requests to L2.
• L2_RQSTS.RFO_HITS — Event 24H, Umask 04H: Counts the number of store RFO requests that hit the L2 cache.

okay back to the event buffet, bestie — we were literally mid-list 💅

• L2_RQSTS.RFO_MISS — (Event 24H, Umask 08H) counts the store RFO requests that miss the L2 cache.
• L2_RQSTS.ALL_RFO — (Event 24H, Umask 0CH) counts all the L2 store RFO requests. every single one, no filter.
• L2_RQSTS.CODE_RD_HIT — (Event 24H, Umask 10H) the number of instruction fetches that hit the L2 cache. slay.
• L2_RQSTS.CODE_RD_MISS — (Event 24H, Umask 20H) the number of instruction fetches that missed the L2 cache 😭.
• L2_RQSTS.ALL_CODE_RD — (Event 24H, Umask 30H) counts all L2 code requests.
• L2_RQSTS.PF_HIT — (Event 24H, Umask 40H) requests from the L2 Hardware prefetcher that hit L2.
• L2_RQSTS.PF_MISS — (Event 24H, Umask 80H) requests from the L2 Hardware prefetcher that missed L2.
• L2_RQSTS.ALL_PF — (Event 24H, Umask C0H) literally any requests from L2 Hardware prefetchers. the whole prefetch friend group 🫶
• L2_STORE_LOCK_RQSTS.MISS — (Event 27H, Umask 01H) RFOs that miss cache lines.
• L2_STORE_LOCK_RQSTS.HIT_E — (Event 27H, Umask 04H) RFOs that hit cache lines in E state.
• L2_STORE_LOCK_RQSTS.HIT_M — (Event 27H, Umask 08H) RFOs that hit cache lines in M state.
• L2_STORE_LOCK_RQSTS.ALL — (Event 27H, Umask 0FH) RFOs that access cache lines in any state. iconic inclusivity.
• L2_L1D_WB_RQSTS.HIT_E — (Event 28H, Umask 04H) not rejected writebacks from L1D to L2 cache lines in E state.
• L2_L1D_WB_RQSTS.HIT_M — (Event 28H, Umask 08H) not rejected writebacks from L1D to L2 cache lines in M state.
• LONGEST_LAT_CACHE.REFERENCE — (Event 2EH, Umask 4FH) counts requests coming from the core that reference a cache line in the last level cache. the final boss of caches 👑
• LONGEST_LAT_CACHE.MISS — (Event 2EH, Umask 41H) counts each cache miss condition for references to the last level cache. every single one 💀
• CPU_CLK_UNHALTED.THREAD_P — (Event 3CH, Umask 00H) counts the number of thread cycles while the thread is not in a halt state. the thread enters the halt state when it's running the HLT instruction. heads up: the core frequency may change from time to time due to power or thermal throttling — so yeah, your numbers can vibe-shift on you 🌡️
• CPU_CLK_THREAD_UNHALTED.REF_XCLK — (Event 3CH, Umask 01H) increments at the frequency of XCLK (100 MHz) when not halted.
• L1D_PEND_MISS.PENDING — (Event 48H, Umask 01H) increments the number of outstanding L1D misses every cycle. set Cmask = 1 and Edge =1 to count occurrences. Counter 2 only; set Cmask = 1 to count cycles. read that twice bestie, it matters 🙈
• DTLB_STORE_MISSES.MISS_CAUSES_A_WALK — (Event 49H, Umask 01H) a miss in all TLB levels that causes a page walk of any page size (4K/2M/4M/1G).
• DTLB_STORE_MISSES.WALK_COMPLETED — (Event 49H, Umask 02H) a miss in all TLB levels that causes a page walk which completes, of any page size (4K/2M/4M/1G).
• DTLB_STORE_MISSES.WALK_DURATION — (Event 49H, Umask 04H) cycles PMH is busy with this walk.
• DTLB_STORE_MISSES.STLB_HIT — (Event 49H, Umask 10H) store operations that miss the first TLB level but hit the second and do not cause page walks. a little win 🎀
• LOAD_HIT_PRE.SW_PF — (Event 4CH, Umask 01H) not SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.
• LOAD_HIT_PER.HW_PF — (Event 4CH, Umask 02H) not SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.
• HW_PRE_REQ.DL1_MISS — (Event 4EH, Umask 02H) Hardware Prefetch requests that miss the L1D cache. a request is being counted each time it accesses the cache & misses it — including if a block is applicable, or if it hit the Fill Buffer, for example. this accounts for both the L1 streamer and IP-based (IPP) HW prefetchers 🧚
• L1D.REPLACEMENT — (Event 51H, Umask 01H) counts the number of lines brought into the L1 data cache.
• L1D.ALLOCATED_IN_M — (Event 51H, Umask 02H) counts the number of allocations of modified L1D cache lines.
• L1D.EVICTION — (Event 51H, Umask 04H) counts the number of modified lines evicted from the L1 data cache due to replacement. bye bestie 👋
• L1D.ALL_M_REPLACEMENT — (Event 51H, Umask 08H) cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.
• PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP — (Event 59H, Umask 20H) increments the number of flags-merge uops in flight each cycle. set Cmask = 1 to count cycles.
• PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW — (Event 59H, Umask 40H) cycles with at least one slow LEA uop allocated.
• PARTIAL_RAT_STALLS.MUL_SINGLE_UOP — (Event 59H, Umask 80H) number of Multiply packed/scalar single precision uops allocated.
• RESOURCE_STALLS2.ALL_FL_EMPTY — (Event 5BH, Umask 0CH) cycles stalled due to free list empty.
• RESOURCE_STALLS2.ALL_PRF_CONTROL — (Event 5BH, Umask 0FH) cycles stalled due to control structures full for physical registers.
• RESOURCE_STALLS2.BOB_FULL — (Event 5BH, Umask 40H) cycles the Allocator is stalled due to the Branch Order Buffer.
• RESOURCE_STALLS2.OOO_RSRC — (Event 5BH, Umask 4FH) cycles stalled due to out of order resources full.
• CPL_CYCLES.RING0 — (Event 5CH, Umask 01H) unhalted core cycles when the thread is in ring 0. use Edge to count transition 👀
• CPL_CYCLES.RING123 — (Event 5CH, Umask 02H) unhalted core cycles when the thread is not in ring 0.
• RS_EVENTS.EMPTY_CYCLES — (Event 5EH, Umask 01H) cycles the RS is empty for the thread.
• OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD — (Event 60H, Umask 01H) offcore outstanding Demand Data Read transactions in SQ to uncore. set Cmask=1 to count cycles.
• OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO — (Event 60H, Umask 04H) offcore outstanding RFO store transactions in SQ to uncore. set Cmask=1 to count cycles.
• OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD — (Event 60H, Umask 08H) offcore outstanding cacheable data read transactions in SQ to uncore. set Cmask=1 to count cycles.
• LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION — (Event 63H, Umask 01H) cycles in which the L1D and L2 are locked, due to a UC lock or split lock.
• LOCK_CYCLES.CACHE_LOCK_DURATION — (Event 63H, Umask 02H) cycles in which the L1D is locked.
• IDQ.EMPTY — (Event 79H, Umask 02H) counts cycles the IDQ is empty.
• IQD.MITE_UOPS — (Event 79H, Umask 04H) increment each cycle # of uops delivered to IDQ from the MITE path. set Cmask = 1 to count cycles. can combine Umask 04H and 20H. (yes, the name really is spelled IQD here — that's the page's spelling, not me being chaotic 💀)
• IDQ.DSB_UOPS — (Event 79H, Umask 08H) increment each cycle. # of uops delivered to IDQ from the DSB path. set Cmask = 1 to count cycles. can combine Umask 08H and 10H.
• IDQ.MS_DSB_UOPS — (Event 79H, Umask 10H) increment each cycle # of uops delivered to IDQ when MS is busy by DSB. set Cmask = 1 to count cycles MS is busy. set Cmask=1 and Edge=1 to count MS activations. can combine Umask 08H and 10H.
• IDQ.MS_MITE_UOPS — (Event 79H, Umask 20H) increment each cycle # of uops delivered to IDQ when MS is busy by MITE. set Cmask = 1 to count cycles. can combine Umask 04H and 20H.
• IDQ.MS_UOPS — (Event 79H, Umask 30H) increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. set Cmask = 1 to count cycles. can combine Umask 04H, 08H and 30H.
• ICACHE.MISSES — (Event 80H, Umask 02H) number of Instruction Cache, Streaming Buffer and Victim Cache Misses. includes UC accesses.
• ITLB_MISSES.MISS_CAUSES_A_WALK — (Event 85H, Umask 01H) misses in all ITLB levels that cause page walks.
• ITLB_MISSES.WALK_COMPLETED — (Event 85H, Umask 02H) misses in all ITLB levels that cause completed page walks.
• ITLB_MISSES.WALK_DURATION — (Event 85H, Umask 04H) cycle PMH is busy with a walk.
• ITLB_MISSES.STLB_HIT — (Event 85H, Umask 10H) number of cache load STLB hits. no page walk. periodt ✨
• ILD_STALL.LCP — (Event 87H, Umask 01H) stalls caused by changing prefix length of the instruction.
• ILD_STALL.IQ_FULL — (Event 87H, Umask 04H) stall cycles due to IQ being full.
• BR_INST_EXEC.NONTAKEN_COND — (Event 88H, Umask 41H) counts conditional near branch instructions that were executed (but not necessarily retired) and not taken.
• BR_INST_EXEC.TAKEN_COND — (Event 88H, Umask 81H) counts conditional near branch instructions that were executed (but not necessarily retired) and taken.
• BR_INST_EXEC.DIRECT_JMP — (Event 88H, Umask 82H) counts all unconditional near branch instructions, excluding calls and indirect branches.
• BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET — (Event 88H, Umask 84H) counts executed indirect near branch instructions that are not calls nor returns.
• BR_INST_EXEC.RETURN_NEAR — (Event 88H, Umask 88H) counts indirect near branches that have a return mnemonic.
• BR_INST_EXEC.DIRECT_NEAR_CALL — (Event 88H, Umask 90H) counts unconditional near call branch instructions, excluding non call branch, executed.
• BR_INST_EXEC.INDIRECT_NEAR_CALL — (Event 88H, Umask A0H) counts indirect near calls, including both register and memory indirect, executed.
• BR_INST_EXEC.ALL_BRANCHES — (Event 88H, Umask FFH) counts all near executed branches (not necessarily retired).
• BR_MISP_EXEC.NONTAKEN_COND — (Event 89H, Umask 41H) counts conditional near branch instructions mispredicted as nontaken 😬
• BR_MISP_EXEC.TAKEN_COND — (Event 89H, Umask 81H) counts conditional near branch instructions mispredicted as taken.
• BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET — (Event 89H, Umask 84H) counts mispredicted indirect near branch instructions that are not calls nor returns.
• BR_MISP_EXEC.RETURN_NEAR — (Event 89H, Umask 88H) counts mispredicted indirect near branches that have a return mnemonic.
• BR_MISP_EXEC.DIRECT_NEAR_CALL — (Event 89H, Umask 90H) counts mispredicted unconditional near call branch instructions, excluding non call branch, executed.
• BR_MISP_EXEC.INDIRECT_NEAR_CALL — (Event 89H, Umask A0H) counts mispredicted indirect near calls, including both register and memory indirect, executed.

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and there's still more where that came from, don't you dare close the tab 🌸

• BR_MISP_EXEC.ALL_BRANCHES — Event 89H, Umask FFH — counts every mispredicted near executed branch (and no, they don't have to be retired, bestie, that's the whole point 💅)
• IDQ_UOPS_NOT_DELIVERED.CORE — Event 9CH, Umask 01H — counts how many uops didn't get delivered to RAT, per thread. Use Cmask to qualify the uop b/w 👑
• UOPS_DISPATCHED_PORT.PORT_0 — Event A1H, Umask 01H — cycles where a uop gets dispatched on port 0.
• UOPS_DISPATCHED_PORT.PORT_1 — Event A1H, Umask 02H — cycles where a uop gets dispatched on port 1.
• UOPS_DISPATCHED_PORT.PORT_2_LD — Event A1H, Umask 04H — cycles where a load uop gets dispatched on port 2 🌸
• UOPS_DISPATCHED_PORT.PORT_2_STA — Event A1H, Umask 08H — cycles where a store address uop gets dispatched on port 2.
• UOPS_DISPATCHED_PORT.PORT_2 — Event A1H, Umask 0CH — cycles where a uop gets dispatched on port 2, any kind.
• UOPS_DISPATCHED_PORT.PORT_3_LD — Event A1H, Umask 10H — cycles where a load uop gets dispatched on port 3.
• UOPS_DISPATCHED_PORT.PORT_3_STA — Event A1H, Umask 20H — cycles where a store address uop gets dispatched on port 3.
• UOPS_DISPATCHED_PORT.PORT_3 — Event A1H, Umask 30H — (Cycles which a Uop is dispatched on port 3.) — yes the original really does wrap the whole thing in parens, we keep the parens, we respect the parens 🫶
• UOPS_DISPATCHED_PORT.PORT_4 — Event A1H, Umask 40H — cycles where a uop gets dispatched on port 4.
• UOPS_DISPATCHED_PORT.PORT_5 — Event A1H, Umask 80H — cycles where a uop gets dispatched on port 5.
• RESOURCE_STALLS.ANY — Event A2H, Umask 01H — cycles where allocation is stalled for any resource-related reason 😭
• RESOURCE_STALLS.LB — Event A2H, Umask 02H — counts stall cycles caused by not having enough load buffers.
• RESOURCE_STALLS.LB — Event A2H, Umask 04H — cycles stalled because no eligible RS entry was available. (And yeah — the page lists RESOURCE_STALLS.LB twice with two different umasks, so here it is twice too. Not a typo on my end, fr fr 💀)
• RESOURCE_STALLS.SB — Event A2H, Umask 08H — cycles stalled because no store buffers were available (and that's not counting draining form sync).
• RESOURCE_STALLS.ROB — Event A2H, Umask 10H — cycles stalled because the re-order buffer was full.
• RESOURCE_STALLS.FCSW — Event A2H, Umask 20H — cycles stalled from writing the FPU control word.
• RESOURCE_STALLS.MXCSR — Event A2H, Umask 40H — cycles stalled because the MXCSR register rename happened too close to a previous MXCSR rename.
• RESOURCE_STALLS.OTHER — Event A2H, Umask 80H — cycles stalled while execution was stuck on other resource issues 🙈
• DSB2MITE_SWITCHES.COUNT — Event ABH, Umask 01H — number of DSB → MITE switches.
• DSB2MITE_SWITCHES.PENALTY_CYCLES — Event ABH, Umask 02H — the cycles of delay those DSB → MITE switches caused ✨
• DSB_FILL.OTHER_CANCEL — Event ACH, Umask 02H — cases where a valid DSB fill got cancelled for some reason other than blowing past the way limit.
• DSB_FILL.EXCEED_DSB_LINES — Event ACH, Umask 08H — DSB Fill hit more than 3 DSB lines.
• DSB_FILL.ALL_CANCEL — Event ACH, Umask 0AH — cases where a valid Decode Stream Buffer (DSB) fill got cancelled, again not because of exceeding the way limit.
• ITLB.ITLB_FLUSH — Event AEH, Umask 01H — counts ITLB flushes, and it covers 4k/2M/4M pages 💖
• OFFCORE_REQUESTS.DEMAND_DATA_RD — Event B0H, Umask 01H — demand data read requests that got sent to uncore.
• OFFCORE_REQUESTS.DEMAND_RFO — Event B0H, Umask 04H — demand RFO read requests sent to uncore, including regular RFOs, locks, and ItoM.
• OFFCORE_REQUESTS.ALL_DATA_RD — Event B0H, Umask 08H — data read requests sent to uncore, both demand and prefetch 🦋
• UOPS_DISPATCHED.THREAD — Event B1H, Umask 01H — counts the total uops to be dispatched per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles 👀
• UOPS_DISPATCHED.CORE — Event B1H, Umask 02H — counts total uops to be dispatched per-core each cycle. You do not need to set ANY.
• OFFCORE_REQUESTS_BUFFER.SQ_FULL — Event B2H, Umask 01H — the offcore requests buffer can't take any more entries for this thread core 😵
• AGU_BYPASS_CANCEL.COUNT — Event B6H, Umask 01H — counts executed load operations that have all of these traits:
  1. addressing of the format [base + offset]
  2. the offset is between 1 and 2047
  3. the address specified in the base register is in one page and the address [base+offset] is in another page
• OFF_CORE_RESPONSE_0 — Event B7H, Umask 01H — Off-core Response Performance Monitoring; PMC0 only. Requires programming MSR 01A6H 🔥
• OFF_CORE_RESPONSE_1 — Event BBH, Umask 01H — Off-core Response Performance Monitoring. PMC3 only. Requires programming MSR 01A7H
• TLB_FLUSH.DTLB_THREAD — Event BDH, Umask 01H — DTLB flush attempts of the thread-specific entries.
• TLB_FLUSH.STLB_ANY — Event BDH, Umask 20H — counts the number of STLB flush attempts.
• L1D_BLOCKS.BANK_CONFLICT_CYCLES — Event BFH, Umask 05H — cycles where dispatched loads get cancelled because of L1D bank conflicts with other load ports. cmask=1
• INST_RETIRED.ANY_P — Event C0H, Umask 00H — number of instructions at retirement 👑
• INST_RETIRED.PREC_DIST — Event C0H, Umask 01H — precise instruction retired event, with hardware to reduce the effect of PEBS shadow in IP distribution. PMC1 only; you must quiesce other PMCs ⚠️
• INST_RETIRED.X87 — Event C0H, Umask 02H — X87 instruction retired event.
• OTHER_ASSISTS.ITLB_MISS_RETIRED — Event C1H, Umask 02H — instructions that experienced an ITLB miss.
• OTHER_ASSISTS.AVX_STORE — Event C1H, Umask 08H — number of assists tied to 256-bit AVX store operations.
• OTHER_ASSISTS.AVX_TO_SSE — Event C1H, Umask 10H — number of transitions from AVX256 to legacy SSE when the penalty applies.
• OTHER_ASSISTS.SSE_TO_AVX — Event C1H, Umask 20H — number of transitions from SSE to AVX-256 when the penalty applies 💫
• UOPS_RETIRED.ALL — Event C2H, Umask 01H — counts the number of micro-ops retired. Use cmask=1 and invert to count active cycles or stalled cycles.
• UOPS_RETIRED.RETIRE_SLOTS — Event C2H, Umask 02H — counts the number of retirement slots used each cycle.
• MACHINE_CLEARS.MEMORY_ORDERING — Event C3H, Umask 02H — counts machine clears caused by memory order conflicts 😤
• MACHINE_CLEARS.SMC — Event C3H, Umask 04H — counts how many times a program writes to a code section.
• MACHINE_CLEARS.MASKMOV — Event C3H, Umask 20H — counts executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.
• BR_INST_RETIRED.ALL_BRANCH — Event C4H, Umask 00H — branch instructions at retirement.
• BR_INST_RETIRED.CONDITIONAL — Event C4H, Umask 01H — counts conditional branch instructions retired.
• BR_INST_RETIRED.NEAR_CALL — Event C4H, Umask 02H — direct and indirect near call instructions retired.
• BR_INST_RETIRED.ALL_BRANCHES — Event C4H, Umask 04H — counts branch instructions retired.
• BR_INST_RETIRED.NEAR_RETURN — Event C4H, Umask 08H — counts near return instructions retired 🎀
• BR_INST_RETIRED.NOT_TAKEN — Event C4H, Umask 10H — counts not-taken branch instructions retired.
• BR_INST_RETIRED.NEAR_TAKEN — Event C4H, Umask 20H — number of near taken branches retired.
• BR_INST_RETIRED.FAR_BRANCH — Event C4H, Umask 40H — number of far branches retired.
• BR_MISP_RETIRED.ALL_BRANCHES — Event C5H, Umask 00H — mispredicted branch instructions at retirement 💀
• BR_MISP_RETIRED.CONDITIONAL — Event C5H, Umask 01H — mispredicted conditional branch instructions retired.
• BR_MISP_RETIRED.NEAR_CALL — Event C5H, Umask 02H — direct and indirect mispredicted near call instructions retired.
• BR_MISP_RETIRED.ALL_BRANCH — Event C5H, Umask 04H — mispredicted macro branch instructions retired.
• BR_MISP_RETIRED.NOT_TAKEN — Event C5H, Umask 10H — mispredicted not-taken branch instructions retired.
• BR_MISP_RETIRED.TAKEN — Event C5H, Umask 20H — mispredicted taken branch instructions retired.
• FP_ASSIST.X87_OUTPUT — Event CAH, Umask 02H — number of X87 assists caused by the output value.
• FP_ASSIST.X87_INPUT — Event CAH, Umask 04H — number of X87 assists caused by the input value.
• FP_ASSIST.SIMD_OUTPUT — Event CAH, Umask 08H — number of SIMD FP assists due to output values.
• FP_ASSIST.SIMD_INPUT — Event CAH, Umask 10H — number of SIMD FP assists due to input values.
• FP_ASSIST.ANY — Event CAH, Umask 1EH — cycles with any input/output SSE* or FP assists 🌈
• ROB_MISC_EVENTS.LBR_INSERTS — Event CCH, Umask 20H — counts the cases where hardware saves new LBR records.
• MEM_TRANS_RETIRED.LOAD_LATENCY — Event CDH, Umask 01H — samples loads with a specified latency threshold. PMC3 only. You specify the threshold in MSR 0x3F6 👈
• MEM_TRANS_RETIRED.PRECISE_STORE — Event CDH, Umask 02H — samples stores and collects precise store operations via PEBS record. PMC3 only.
• MEM_UOP_RETIRED.LOADS — Event D0H, Umask 01H — qualifies retired memory uops that are loads. Combine with umask 10H, 20H, 40H, 80H.
• MEM_UOP_RETIRED.STORES — Event D0H, Umask 02H — qualifies retired memory uops that are stores. Combine with umask 10H, 20H, 40H, 80H.
• MEM_UOP_RETIRED.STLB_MISS — Event D0H, Umask 10H — qualifies retired memory uops with an STLB miss. Must combine with umask 01H, 02H to produce counts.
• MEM_UOP_RETIRED.LOCK — Event D0H, Umask 20H — qualifies retired memory uops that have a lock. Must combine with umask 01H, 02H to produce counts.
• MEM_UOP_RETIRED.SPLIT — Event D0H, Umask 40H — qualifies retired memory uops with a line split. Must combine with umask 01H, 02H to produce counts.
• MEM_UOP_RETIRED_ALL — Event D0H, Umask 80H — qualifies any retired memory uops. Must combine with umask 01H, 02H to produce counts 🫶
• MEM_LOAD_UOPS_RETIRED.L1_HIT — Event D1H, Umask 01H — retired load uops with L1 cache hits as their data sources. Must combine with umask 01H, 02H to produce counts ✨
• MEM_LOAD_UOPS_RETIRED.L2_HIT — (Event D1H, Umask 02H) retired load uops whose data sources were L2 cache hits. cute, close, fast. 💖
• MEM_LOAD_UOPS_RETIRED.LLC_HIT — (Event D1H, Umask 04H) retired load uops whose data sources were data hits in the LLC with no snoops required. no drama, no cross-core gossip. ✨
• MEM_LOAD_UOPS_RETIRED.HIT_LFB — (Event D1H, Umask 40H) retired load uops whose data sources were load uops that missed L1 but hit FB, because a preceding miss to the same cache line had its data not ready yet. it's giving "waiting in the group chat for someone to send the screenshot." 😭
• MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS — (Event D2H, Umask 01H) retired load uops whose data sources were an LLC hit with a cross-core snoop that missed in an on-pkg core cache. 💅
• MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT — (Event D2H, Umask 02H) retired load uops whose data sources were LLC and cross-core snoop hits in an on-pkg core cache. she found it AND it was mutual. 🫶
• MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM — (Event D2H, Umask 04H) retired load uops whose data sources were HitM responses from the shared LLC. main character cache line, honestly. 👑
• MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE — (Event D2H, Umask 08H) retired load uops whose data sources were hits in the LLC with no snoops required. lowkey the chillest one here. 🌸
• MEM_LOAD_UOPS_LLC_HIT_RETIRED.LLC_MISS — (Event D4H, Umask 02H) retired load uops with unknown information as the data source in the cache that serviced the load. literally "idk her" energy. 🙈
• L2_TRANS.DEMAND_DATA_RD — (Event F0H, Umask 01H) demand Data Read requests that access the L2 cache. 📥
• L2_TRANS.RF0 — (Event F0H, Umask 02H) RFO requests that access the L2 cache. (yes, RF0 with a zero, that's how it's spelled here — don't come for me, I'm just the messenger 💀)
• L2_TRANS.CODE_RD — (Event F0H, Umask 04H) L2 cache accesses when fetching instructions. brain food. 🧚
• L2_TRANS.ALL_PF — (Event F0H, Umask 08H) L2 or LLC hardware prefetches that access the L2 cache. manifesting the data before you even ask. ✨
• L2_TRANS.L1D_WB — (Event F0H, Umask 10H) L1D writebacks that access the L2 cache. 📤
• L2_TRANS.L2_FILL — (Event F0H, Umask 20H) L2 fill requests that access the L2 cache. 🍓
• L2_TRANS.L2_WB — (Event F0H, Umask 40H) L2 writebacks that access the L2 cache. 💌
• L2_TRANS.ALL_REQUESTS — (Event F0H, Umask 80H) transactions accessing the L2 pipe. the whole friend group, all at once. 🌈
• L2_LINES_IN.I — (Event F1H, Umask 01H) L2 cache lines in the I state filling the L2. Counting does not cover rejects. 🎀
• L2_LINES_IN.S — (Event F1H, Umask 02H) L2 cache lines in the S state filling the L2. Counting does not cover rejects. 💜
• L2_LINES_IN.E — (Event F1H, Umask 04H) L2 cache lines in the E state filling the L2. Counting does not cover rejects. ⭐
• L2_LINES-IN.ALL — (Event F1H, Umask 07H) L2 cache lines filling the L2. Counting does not cover rejects. and yes bestie, that's a hyphen in the name, not a dot — I am copying it exactly as it's written, do not @ me. 😭
• L2_LINES_OUT.DEMAND_CLEAN — (Event F2H, Umask 01H) clean L2 cache lines evicted by demand. she left on her own terms. 💅
• L2_LINES_OUT.DEMAND_DIRTY — (Event F2H, Umask 02H) dirty L2 cache lines evicted by demand. messy exit, but make it demand. 💀
• L2_LINES_OUT.PF_CLEAN — (Event F2H, Umask 04H) clean L2 cache lines evicted by an L2 prefetch. 🌸
• L2_LINES_OUT.PF_DIRTY — (Event F2H, Umask 08H) dirty L2 cache lines evicted by an L2 prefetch. 🙈
• L2_LINES_OUT.DIRTY_ALL — (Event F2H, Umask 0AH) dirty L2 cache lines filling the L2. Counting does not cover rejects. note the umask is 0AH — that's a letter A, bestie, not a typo. 🔥
• SQ_MISC.SPLIT_LOCK — (Event F4H, Umask 10H) split locks in the SQ. the final boss of this list. 👑

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🌟 SEE ALSO 🌟

okay so these are the other pages you should go read next, and honestly they're all a vibe:

• pmc(3)
• pmc.amd(3)
• pmc.atom(3)
• pmc.core(3)
• pmc.corei7(3)
• pmc.corei7uc(3)
• pmc.iaf(3)
• pmc.ivybridge(3)
• pmc.ivybridgexeon(3)
• pmc.sandybridgeuc(3)
• pmc.sandybridgexeon(3)
• pmc.soft(3)
• pmc.tsc(3)
• pmc.ucf(3)
• pmc.westmere(3)
• pmc.westmereuc(3)
• pmc_cpuinfo(3)
• pmclog(3)
• hwpmc(4)

like, go read them, i'll wait. 💖

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🕰️ HISTORY 🕰️

The pmc library first appeared in FreeBSD 6.0. vintage. iconic. a whole elder statesman. ✨

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🫶 AUTHORS 🫶

The Performance Counters Library (libpmc, -lpmc) library was written by Joseph Koshy <jkoshy@FreeBSD.org>. 📝

The support for the Sandy Bridge microarchitecture was written by Davide Italiano <davide@FreeBSD.org>. 👏

put some respect on their names, fr fr. 🎀

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💜 and that's a wrap on the whole page, bestie! this one comes from Debian, dated October 19, 2012 — yes, she's a lil vintage, and she still ate. go count some L2 lines for me, ily, bye! 🦋🌸💅