e1000_set_lplu_state_pchlan(9)
π e1000_set_lplu_state_pchlan(9) β the manual page bestie π
okay so welcome to the e1000_set_lplu_state_pchlan(9) page, this is the kernel API manual and we're gonna get you fluent in it, no cap β¨
πΈ NAME πΈ
e1000_set_lplu_state_pchlan β Set Low Power Link Up state π¦
like, that's literally the whole vibe. it sets the LPLU state. she's an icon, she's a one-liner.
β¨ SYNOPSIS β¨
s32 e1000_set_lplu_state_pchlan (struct e1000_hw *hw , bool active );
copy that exactly, don't be out here retyping it from memory bestie π
π ARGUMENTS π
hwβ pointer to the HW structure π that's your hardware handle, she's the main character hereactiveβtrueto enable LPLU,falseto disable π«Ά like a light switch but make it networking
π₯ DESCRIPTION π₯
okay so the tea: this function sets the LPLU state according to the active flag. periodt. β¨
but here's where it gets juicy π β for PCH, if the OEM write bit are disabled in the NVM, writing the LPLU bits in the MAC will not set the phy speed. not me finding out the hardware just ignores you like that π so this function steps in and manually sets the LPLU bit and restarts auto-neg as hw would do. she does it herself. independent queen behavior π
and then the cute part: D3 and D0 LPLU will call the same function since it configures the same bit. one function, two power states, zero duplication β that's efficiency, that's range, that's eating πβ
π SEE ALSO π
this list is LONG bestie, but every single one of these is getting its moment, i'm not skipping a single soul π here we go, in order:
e1000_phy_is_accessible_pchlan(9)e1000_toggle_lanphypc_pch_lpt(9)e1000_reconfigure_k1_params(9)e1000_init_phy_workarounds_pchlan(9)e1000_init_phy_params_pchlan(9)e1000_init_phy_params_ich8lan(9)e1000_init_nvm_params_ich8lan(9)e1000_init_mac_params_ich8lan(9)__e1000_access_emi_reg_locked(9)e1000_read_emi_reg_locked(9)e1000_write_emi_reg_locked(9)e1000_set_eee_pchlan(9)e1000_k1_workaround_lpt_lp(9)e1000_platform_pm_pch_lpt(9)e1000e_force_smbus(9)e1000_enable_ulp_lpt_lp(9)e1000_disable_ulp_lpt_lp(9)e1000_check_for_copper_link_ich8lan(9)e1000_acquire_nvm_ich8lan(9)e1000_release_nvm_ich8lan(9)e1000_acquire_swflag_ich8lan(9)e1000_release_swflag_ich8lan(9)e1000_check_mng_mode_ich8lan(9)e1000_check_mng_mode_pchlan(9)e1000_rar_set_pch2lan(9)e1000_rar_get_count_pch_lpt(9)e1000_rar_set_pch_lpt(9)e1000_check_reset_block_ich8lan(9)e1000_write_smbus_addr(9)e1000_sw_lcd_config_ich8lan(9)e1000_k1_gig_workaround_hv(9)e1000_configure_k1_ich8lan(9)e1000_oem_bits_config_ich8lan(9)e1000_set_mdio_slow_mode_hv(9)e1000_hv_phy_workarounds_ich8lan(9)e1000_copy_rx_addrs_to_phy_ich8lan(9)e1000_lv_jumbo_workaround_ich8lan(9)e1000_lv_phy_workarounds_ich8lan(9)e1000_k1_workaround_lv(9)e1000_gate_hw_phy_config_ich8lan(9)e1000_lan_init_done_ich8lan(9)e1000_post_phy_reset_ich8lan(9)e1000_phy_hw_reset_ich8lan(9)e1000_set_d0_lplu_state_ich8lan(9)e1000_set_d3_lplu_state_ich8lan(9)e1000_valid_nvm_bank_detect_ich8lan(9)e1000_read_nvm_spt(9)e1000_read_nvm_ich8lan(9)e1000_flash_cycle_init_ich8lan(9)e1000_flash_cycle_ich8lan(9)e1000_read_flash_dword_ich8lan(9)e1000_read_flash_word_ich8lan(9)e1000_read_flash_byte_ich8lan(9)e1000_read_flash_data_ich8lan(9)e1000_read_flash_data32_ich8lan(9)e1000_write_nvm_ich8lan(9)e1000_update_nvm_checksum_spt(9)e1000_update_nvm_checksum_ich8lan(9)e1000_validate_nvm_checksum_ich8lan(9)e1000e_write_protect_nvm_ich8lan(9)e1000_write_flash_data_ich8lan(9)e1000_write_flash_data32_ich8lan(9)e1000_write_flash_byte_ich8lan(9)e1000_retry_write_flash_dword_ich8lan(9)e1000_retry_write_flash_byte_ich8lan(9)e1000_erase_flash_bank_ich8lan(9)e1000_valid_led_default_ich8lan(9)e1000_id_led_init_pchlan(9)e1000_get_bus_info_ich8lan(9)e1000_reset_hw_ich8lan(9)e1000_init_hw_ich8lan(9)e1000_initialize_hw_bits_ich8lan(9)e1000_setup_link_ich8lan(9)e1000_setup_copper_link_ich8lan(9)e1000_setup_copper_link_pch_lpt(9)e1000_get_link_up_info_ich8lan(9)e1000_kmrn_lock_loss_workaround_ich8lan(9)e1000e_set_kmrn_lock_loss_workaround_ich8lan(9)e1000e_igp3_phy_powerdown_workaround_ich8lan(9)e1000e_gig_downshift_workaround_ich8lan(9)e1000_suspend_workarounds_ich8lan(9)e1000_resume_workarounds_pchlan(9)e1000_cleanup_led_ich8lan(9)e1000_led_on_ich8lan(9)e1000_led_off_ich8lan(9)e1000_setup_led_pchlan(9)e1000_cleanup_led_pchlan(9)e1000_led_on_pchlan(9)e1000_led_off_pchlan(9)e1000_get_cfg_done_ich8lan(9)e1000_power_down_phy_copper_ich8lan(9)e1000_clear_hw_cntrs_ich8lan(9)
also the kernel file itself lives at ./drivers/net/ethernet/intel/e1000e/ich8lan.c β that's where the source material is, go read her if you want the deep lore ππ
ok real talk for a sec π«Ά this page is from the Kernel API Manual, dated October 2026, and the source lives in ./drivers/net/ethernet/intel/e1000e/ich8lan.c. that's the version/source + date tea, mentioned with love, and now we're done bestie π
β¨π
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms