e1000_platform_pm_pch_lpt(9)
π e1000_platform_pm_pch_lpt(9) β from the Kernel API Manual, bestie π
okay so picture this: you're deep in the kernel, section 9, and the manual page you've got open is literally called e1000_platform_pm_pch_lpt(9). yes that's a mouthful, no we're not shortening it, it's iconic and we respect it. let's get into it β¨
πΈ NAME πΈ
e1000_platform_pm_pch_lpt β sets the platform power management values. that's the whole vibe. she does one thing and she does it well π
β¨ SYNOPSIS β¨
s32 e1000_platform_pm_pch_lpt (struct e1000_hw *hw , bool link );
look at her. s32 in, s32 out, two args, no drama π«Ά
π ARGUMENTS π
hwβ pointer to theHWstructure, aka the whole hardware situation. bestie needs to know what she's working with πlinkβ aboolindicating link status. basically: is the link up or not. that's the tea β
π¦ DESCRIPTION π¦
okay so what she actually does π β she sets the Latency Tolerance Reporting (LTR) values for the "PCIe-like" GbE MAC in the Lynx Point PCH.
and how does she decide those values? based on the Rx buffer size and the link speed β but only when link is up. and even then, those values must not exceed the maximum latency supported by the platform (read that again, it's important, no cap π«£). if the link is not up, she just specifies that there is no LTR requirement. simple as that β¨
now here's the part that's lowkey fascinating and you need to hear it π β unlike true-PCIe devices, which set the LTR maximum snoop/no-snoop latencies in the LTR Extended Capability Structure inside the PCIe Extended Capability register set, on this device LTR is set a completely different way:
- she writes the equivalent snoop/no-snoop latencies into the
LTRVregister in the MAC, and - she sets the
SENDbit, which fires off an Intel On-chip System Fabric sideband (IOSF-SB) message to the PMC π
it's giving "not like other devices" and honestly? slay π₯
π SEE ALSO π
the kernel file, first of all:
- Kernel file
./drivers/net/ethernet/intel/e1000e/ich8lan.c
and now the full friend group, everybody say hi π (yes, all of them, we're not leaving anyone out, that would be mean):
e1000_phy_is_accessible_pchlan(9)e1000_toggle_lanphypc_pch_lpt(9)e1000_reconfigure_k1_params(9)e1000_init_phy_workarounds_pchlan(9)e1000_init_phy_params_pchlan(9)e1000_init_phy_params_ich8lan(9)e1000_init_nvm_params_ich8lan(9)e1000_init_mac_params_ich8lan(9)__e1000_access_emi_reg_locked(9)e1000_read_emi_reg_locked(9)e1000_write_emi_reg_locked(9)e1000_set_eee_pchlan(9)e1000_k1_workaround_lpt_lp(9)e1000e_force_smbus(9)e1000_enable_ulp_lpt_lp(9)e1000_disable_ulp_lpt_lp(9)e1000_check_for_copper_link_ich8lan(9)e1000_acquire_nvm_ich8lan(9)e1000_release_nvm_ich8lan(9)e1000_acquire_swflag_ich8lan(9)e1000_release_swflag_ich8lan(9)e1000_check_mng_mode_ich8lan(9)e1000_check_mng_mode_pchlan(9)e1000_rar_set_pch2lan(9)e1000_rar_get_count_pch_lpt(9)e1000_rar_set_pch_lpt(9)e1000_check_reset_block_ich8lan(9)e1000_write_smbus_addr(9)e1000_sw_lcd_config_ich8lan(9)e1000_k1_gig_workaround_hv(9)e1000_configure_k1_ich8lan(9)e1000_oem_bits_config_ich8lan(9)e1000_set_mdio_slow_mode_hv(9)e1000_hv_phy_workarounds_ich8lan(9)e1000_copy_rx_addrs_to_phy_ich8lan(9)e1000_lv_jumbo_workaround_ich8lan(9)e1000_lv_phy_workarounds_ich8lan(9)e1000_k1_workaround_lv(9)e1000_gate_hw_phy_config_ich8lan(9)e1000_lan_init_done_ich8lan(9)e1000_post_phy_reset_ich8lan(9)e1000_phy_hw_reset_ich8lan(9)e1000_set_lplu_state_pchlan(9)e1000_set_d0_lplu_state_ich8lan(9)e1000_set_d3_lplu_state_ich8lan(9)e1000_valid_nvm_bank_detect_ich8lan(9)e1000_read_nvm_spt(9)e1000_read_nvm_ich8lan(9)e1000_flash_cycle_init_ich8lan(9)e1000_flash_cycle_ich8lan(9)e1000_read_flash_dword_ich8lan(9)e1000_read_flash_word_ich8lan(9)e1000_read_flash_byte_ich8lan(9)e1000_read_flash_data_ich8lan(9)e1000_read_flash_data32_ich8lan(9)e1000_write_nvm_ich8lan(9)e1000_update_nvm_checksum_spt(9)e1000_update_nvm_checksum_ich8lan(9)e1000_validate_nvm_checksum_ich8lan(9)e1000e_write_protect_nvm_ich8lan(9)e1000_write_flash_data_ich8lan(9)e1000_write_flash_data32_ich8lan(9)e1000_write_flash_byte_ich8lan(9)e1000_retry_write_flash_dword_ich8lan(9)e1000_retry_write_flash_byte_ich8lan(9)e1000_erase_flash_bank_ich8lan(9)e1000_valid_led_default_ich8lan(9)e1000_id_led_init_pchlan(9)e1000_get_bus_info_ich8lan(9)e1000_reset_hw_ich8lan(9)e1000_init_hw_ich8lan(9)e1000_initialize_hw_bits_ich8lan(9)e1000_setup_link_ich8lan(9)e1000_setup_copper_link_ich8lan(9)e1000_setup_copper_link_pch_lpt(9)e1000_get_link_up_info_ich8lan(9)e1000_kmrn_lock_loss_workaround_ich8lan(9)e1000e_set_kmrn_lock_loss_workaround_ich8lan(9)e1000e_igp3_phy_powerdown_workaround_ich8lan(9)e1000e_gig_downshift_workaround_ich8lan(9)e1000_suspend_workarounds_ich8lan(9)e1000_resume_workarounds_pchlan(9)e1000_cleanup_led_ich8lan(9)e1000_led_on_ich8lan(9)e1000_led_off_ich8lan(9)e1000_setup_led_pchlan(9)e1000_cleanup_led_pchlan(9)e1000_led_on_pchlan(9)e1000_led_off_pchlan(9)e1000_get_cfg_done_ich8lan(9)e1000_power_down_phy_copper_ich8lan(9)e1000_clear_hw_cntrs_ich8lan(9)
and that's the whole page, bestie π every flag, every friend, no crumbs left behind π
kisses and goodnight ππ β this one came out of the kernel source at ./drivers/net/ethernet/intel/e... and is dated October 2026, and yes she's still signed e1000_platform_pm_pch_lpt(9) because legends never change their name πβ¨π§
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms